US 12,567,450 B2 · MRAM circuit and layout

Abstract

A MRAM circuit is provided in the present invention, wherein each memory cell has three transistors, including a first transistor, a third transistor and a second transistor connected in order and series connection, a first node is connected between the first transistor and the third transistor, a second node is connected between the second transistor and the third transistor, and a common source line is connected with one terminal of the first transistor and the second transistor. A first MTJ set includes at least two MTJs in series connection and with one terminal connected to the first node, and a second MTJ set includes at least two MTJs in series connection and with one terminal connected to the second node.

Claims17

Dependent claims

A MRAM circuit with multiple memory cells, wherein each of said memory cells comprises:

three transistors, comprising a first transistor, a third transistor and a second transistor in order and series connection, wherein a junction directly connecting said first transistor to said third transistor is a first node, a junction directly connecting said second transistor to said third transistor is a second node, one terminal of each of said first transistor and said second transistor is connected to a common source line;
a first MTJ set, comprising at least two MTJs connected in series with one terminal connecting to said first node;
and
a second MTJ set, comprising at least two MTJs connected in series with one terminal connecting to said second node.

1 more element

A MRAM layout with multiple memory cells on a substrate, and said substrate is provided with multiple active areas arranged in a first direction, wherein each of said memory cells comprises:

a first word line, a third word line and a second word line arranged sequentially and spaced-apart on said substrate and extending in a second direction over said active areas, wherein an active area at outer side of said first word line is first active area, an active area between said first word line and said third word line is second active area, an active area between said second word line and said third word line is third active area, and an active area at outer side of said second word line is fourth active area;
a first MTJ set, comprising at least two MTJs connected in series between a first terminal and a second terminal at different levels of BEOL metal layers and with the first terminal connected to said second active area;
a second MTJ set, comprising at least two MTJs connected in series between a third terminal and a fourth terminal at different levels of said BEOL metal layers and with the third terminal connected to said third active area;
a first bit line, connected to the second terminal of said first MTJ set;
and
a second bit line, connected to the fourth terminal of said second MTJ set, wherein one of the second terminal or the fourth terminal is directly connected to a bit line.

3 more elements

Dependencies are inferred from the claim text.

MRAM circuit and layout

Life of this patent

MRAM circuit and layout

Life of this patent

Abstract

Claims17