Semiconductor device having output buffer

An apparatus, comprising:

• a semiconductor substrate having a plurality of source regions and a plurality of drain regions alternately arranged in a first direction;
• a plurality of gate electrodes covering the semiconductor substrate each located between an associated one of the plurality of source regions and an associated one of the plurality of drain regions;
• a first wiring layer including a plurality of first conductive patterns each covering an associated one of the plurality of source regions, and the first wiring layer further including a plurality of second conductive patterns each covering an associated one of the plurality of drain regions;
• a plurality of first via conductors each connected between an associated one of the plurality of first conductive patterns and an associated one of the plurality of source regions;
• a plurality of second via conductors each connected between an associated one of the plurality of second conductive patterns and an associated one of the plurality of drain regions;
• a second wiring layer located over the first wiring layer, the second wiring layer including a plurality of third conductive patterns each covering an associated one of the plurality of first conductive patterns, and the second wiring layer further including a plurality of fourth conductive patterns each covering an associated one of the plurality of second conductive patterns;
• a plurality of third via conductors each connected between an associated one of the plurality of third conductive patterns and an associated one of the plurality of first conductive patterns;
• and
• a plurality of fourth via conductors each connected between an associated one of the plurality of fourth conductive patterns and an associated one of the plurality of second conductive patterns, wherein
• the plurality of third via conductors are arranged in line in the first direction,
• the plurality of fourth via conductors are arranged in line in the first direction,
• the plurality of fourth via conductors are shifted from the plurality of third via conductors in a second direction perpendicular to the first direction, and
• the plurality of third and fourth via conductors are arranged in a zigzag manner.

An apparatus, comprising:

• a semiconductor substrate including a plurality of source regions and a plurality of drain regions alternately arranged in a first direction;
• a plurality of gate electrodes above the semiconductor substrate and each between an associated one of the plurality of source regions and an associated one of the plurality of drain regions;
• a first wiring layer including:
• a plurality of first conductive patterns each coupled to an associated one of the plurality of source regions by an associated one of a plurality of first via conductors;
• and
• a plurality of second conductive patterns each coupled to an associated one of the plurality of drain regions by an associated one of a plurality of second via conductors;
• and
• a second wiring layer above the first wiring layer, the second wiring layer including:
• a plurality of third conductive patterns each coupled to an associated one of the plurality of first conductive patterns by an associated one of a plurality of third via conductors;
• and
• a plurality of fourth conductive patterns each coupled to an associated one of the plurality of second conductive patterns by an associated one of a plurality of fourth via conductors,
• wherein
• the plurality of fourth via conductors are shifted from the plurality of third via conductors in a second direction perpendicular to the first direction.