Integrated circuit, chip, and electronic device

A chip, comprising:

• D dice, wherein the D dice comprise:
• a first die comprising a first tile array;
• a second die comprising a second tile array, wherein an arrangement of the first tile array on the first die and an arrangement of the second tile array on the second die are rotationally symmetrical;
• a third die comprising a third tile array;
• and
• a fourth die comprising a fourth tile array, wherein an arrangement of the third tile array on the third die and an arrangement of the fourth tile array on the fourth die are rotationally symmetrical, and wherein:
• the first tile array comprises N×M tiles, N is a positive integer greater than or equal to 2, and M is a positive integer greater than or equal to 2;
• the second tile array comprises N×M tiles;
• the third tile array comprises N×M tiles;
• the fourth tile array comprises N×M tiles;
• the first die further comprises N groups of first row buses and M groups of first column buses;
• the second die further comprises N groups of second row buses and M groups of second column buses;
• the third die further comprises N groups of third row buses and M groups of third column buses;
• the fourth die further comprises N groups of fourth row buses and M groups of fourth column buses;
• an nth group of first row buses in the N groups of first row buses is connected to an nth group of third row buses in the N groups of third row buses, and n is a positive integer greater than or equal to 1 and less than or equal to N;
• an mth group of first column buses in the M groups of first column buses is connected to an mth group of fourth column buses in the M groups of fourth column buses, and m is a positive integer greater than or equal to 1 and less than or equal to M;
• an nth group of fourth row buses in the N groups of fourth row buses is connected to an nth group of second row buses in the N groups of second row buses;
• an mth group of third column buses in the M groups of third column buses is connected to an mth group of second column buses in the M groups of second column buses;
• the mth group of first column buses in the M groups of first column buses comprises N groups of first transmission lines and N groups of second transmission lines, each group of transmission lines in the N groups of first transmission lines and the N groups of second transmission lines comprises K transmission line subgroups, a first interface of an nth tile in an mth column of tiles in the first tile array comprises a first sending interface and a first receiving interface, the first sending interface is connected to the N groups of first transmission lines, and the first receiving interface is connected to an nth group of second transmission lines in the N groups of second transmission lines;
• the mth group of fourth column buses in the M groups of fourth column buses comprises N groups of third transmission lines and N groups of fourth transmission lines, each group of transmission lines in the N groups of third transmission lines and the N groups of fourth transmission lines comprises K transmission line subgroups, a second interface of an nth tile in an mth column of tiles in the fourth tile array comprises a second sending interface and a second receiving interface, the second sending interface is connected to the N groups of third transmission lines, and the second receiving interface is connected to an nth group of fourth transmission lines in the N groups of fourth transmission lines;
• and
• the N groups of first transmission lines are connected to the N groups of third transmission lines, and the N groups of second transmission lines are connected to the N groups of fourth transmission lines.

A chip, comprising:

• D dice, wherein the D dice comprise:
• a first die comprising a first tile array;
• a second die comprising a second tile array, wherein an arrangement of the first tile array on the first die and an arrangement of the second tile array on the second die are rotationally symmetrical, and wherein:
• the first tile array comprises N×M tiles, N is a positive integer greater than or equal to 2, and M is a positive integer greater than or equal to 2;
• the second tile array comprises N×M tiles;
• the first die further comprises N groups of first row buses and M groups of first column buses;
• the second die comprises N groups of second row buses and M groups of second column buses;
• an mth group of first column buses in the M groups of first column buses is connected to an mth group of second column buses in the M groups of second column buses, and m is a positive integer greater than or equal to 1 and less than or equal to M;
• the mth group of first column buses in the M groups of first column buses comprises N groups of first transmission lines and N groups of second transmission lines, each group of transmission lines in the N groups of first transmission lines and the N groups of second transmission lines comprises K transmission line subgroups, a first interface of an nth tile in an mth column of tiles in the first tile array comprises a first sending interface and a first receiving interface, the first sending interface is connected to the N groups of first transmission lines, and the first receiving interface is connected to an nth group of second transmission lines in the N groups of second transmission lines;
• the mth group of second column buses in the M groups of second column buses comprises N groups of third transmission lines and N groups of fourth transmission lines, each group of transmission lines in the N groups of third transmission lines and the N groups of fourth transmission lines comprises K transmission line subgroups, a second interface of an nth tile in an mth column of tiles in the second tile array comprises a second sending interface and a second receiving interface, the second sending interface is connected to the N groups of third transmission lines, and the second receiving interface is connected to an nth group of fourth transmission lines in the N groups of fourth transmission lines;
• and
• the N groups of first transmission lines are connected to the N groups of third transmission lines, and the N groups of second transmission lines are connected to the N groups of fourth transmission lines.