Systems and methods for cache analysis and management
AssigneeTrustees of Tufts College
InventorsCesar Gomes, Maziar Mehdizadehamiraski, Mark Hempstead
Life of this patent
Estimating the term…
Abstract
Systems, methods, and media for managing a shared memory cache in a computing system. The management of the shared memory cache can include, for example, determining cache statistics by probabilistically sampling the memory cache: estimating contention of the memory cache based on capturing theft-based contention; and re-partitioning the memory cache based on the cache statistics and the estimated contention. The cache statistics can include thefts and interferences associated with a plurality of cores of the computing system.
Claims20
A method of managing a shared memory cache in a computing system, the method comprising:
- determining cache statistics associated with the shared memory cache by probabilistically sampling the shared memory cache, the cache statistics comprising thefts and interferences associated with a plurality of cores of the computing system, the thefts comprising instances in which at least one block of the shared memory cache that is associated with one of the plurality of cores causes eviction of another block of the shared memory cache that is associated with another of the plurality of cores, the interferences comprising instances in which at least one block of the shared memory cache that is associated with one of the plurality of cores is evicted by another block of the shared memory cache that is associated with another of the plurality of cores;
- estimating contention of the memory cache based on the cache statistics comprising the thefts and the interferences associated with the plurality of cores of the computing system;
- and
- re-partitioning the shared memory cache among the plurality of cores based on the cache statistics and the estimated contention.
A computing system comprising:
- a partitioned memory cache that is shared among and in communication with a plurality of cores;
- and
- a processor comprising the plurality of cores and configured to:
- determine cache statistics by probabilistically sampling the partitioned memory cache, the cache statistics comprising thefts and interferences associated with the plurality of cores, the thefts comprising instances in which at least one block of the partitioned memory cache that is associated with one of the plurality of cores causes eviction of another block of the partitioned memory cache that is associated with another of the plurality of cores, the interferences comprising instances in which at least one block of the partitioned memory cache that is associated with one of the plurality of cores is evicted by another block of the partitioned memory cache that is associated with another of the plurality of cores;
- estimate contention of the partitioned memory cache based on the cache statistics comprising the thefts and the interferences associated with the plurality of cores;
- and
- re-partition the partitioned memory cache among the plurality of cores, based on the cache statistics and the estimated contention.
A non-transitory computer-readable storage medium having instructions stored thereon that, when executed by a processor, cause the processor to:
- determine cache statistics associated with a memory cache by probabilistically sampling the memory cache, the memory cache in communication with and shared among a plurality of cores of the processor, the cache statistics comprising thefts and interferences associated with the plurality of cores, the thefts comprising instances in which at least one block of the memory cache that is associated with one of the plurality of cores causes eviction of another block of the memory cache that is associated with another of the plurality of cores, the interferences comprising instances in which at least one block of the memory cache that is associated with one of the plurality of cores is evicted by another block of the memory cache that is associated with another of the plurality of cores;
- estimate contention of the memory cache based on the cache statistics comprising the thefts and the interferences associated with the plurality of cores;
- and
- re-partition the memory cache among the plurality of cores based on the cache statistics and the estimated contention.
Dependencies are inferred from the claim text.