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US 12,566,613 B2Granted
Microprocessor with speculative and in-order register sets
AssigneeSimplex Micro, Inc.
InventorThang Minh Tran
Life of this patent
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Abstract
A processor includes a time counter and a time-resource matrix and statically dispatches speculative and in-order instructions. The time counter increments periodically, for example, every clock cycle, and the resulting count is used to statically schedule instruction execution. The processor includes a speculative register rename unit and a non-speculative register rename unit to allow certain types of instructions to be executed speculatively while other instructions are executed non-speculatively.
Claims15
A processor comprising:
- a time counter storing a time count representing a current time of the processor, wherein the time count is incremented periodically;
- a register renaming unit comprising,
- a register free list that identifies a plurality of temporary registers wherein a first temporary register is used to rename a first destination register of a first speculative instruction;
- a register alias table that identifies for each architectural register of the processor wherein the first destination register is renamed to the first temporary register at issuance of the first speculative instruction;
- an architectural register table that identifies each architectural register of the processor wherein the first destination register is renamed to the first temporary register at retiring of the first speculative instruction and wherein a previous renamed register of the first destination register is released to the register free list as a temporary register;
- an instruction issue unit that is coupled to the time counter and receives the first speculative instruction and wherein the first destination register of the first speculative instruction is renamed with the first temporary register of the register free list;
- a register scoreboard coupled to the time counter and the instruction issue unit and the register renaming unit to record a write back time of the first temporary register;
- a first execution queue coupled to the time counter and the instruction issue unit to receive the first speculative instruction from the instruction issue unit, and dispatch the first speculative instruction to a first functional unit at a first preset execution time that corresponds to a first time count and wherein the first functional unit writes a result data to the first temporary register of a register file;
- wherein the instruction issue unit receives a second non-speculative instruction and issues the second non-speculative instruction wherein a second destination register of the second non-speculative instruction references a renamed register from the register alias table and wherein the second non-speculative instruction is issued to the execution queue when the second non-speculative instruction cannot be cancelled;
- a read control unit having registers storing time count entries specifying when operands may be read and transported on a read bus, and wherein the read control unit further accesses the register scoreboard to determine availability of a first register in a register file, wherein if a write time of the first register is the same as the time count then data is forwarded instead of being read from the register file;
- and
- a write control unit having write bus control registers storing time count entries specifying when result data may be transported on a write bus and written to a second register of the register file, and wherein the write control unit further accesses the register scoreboard to clear a valid bit if a write time stored in a write bus control register of the write bus control registers is the same as the time count.
9 more elements
A processor comprising:
- a clock circuit;
- a time counter storing a time count representing a specific time of operation of the processor, wherein the time count is incremented by the clock circuit;
- a plurality of architectural registers;
- a first register renaming unit comprising
- a register free list for temporary registers, each temporary register used to rename a destination register of a first speculative instruction,
- a register alias table that tracks register renaming of the architectural registers upon issuance of a speculative instruction, and
- an architectural register table that tracks register renaming of the architectural registers upon retiring an instruction;
- a second register renaming unit that renames a destination register of a second instruction wherein contents of the second register renaming unit are copied to the first register renaming unit if the first speculative instruction encounters a branch misprediction or an exception;
- a register scoreboard coupled to the time counter to record a write back time of a destination register and a read time of a source register referenced by the first speculative instruction;
- a time-resource matrix coupled to the register scoreboard and the time counter for storing information relating to available resources for each time count of the time counter;
- a first execution queue coupled to the time counter and an instruction issue unit to receive the first speculative instruction from the instruction issue unit, and dispatch the first speculative instruction to a first functional unit when the first preset execution time corresponds to the time count;
- wherein the instruction issue unit receives a second non-speculative instruction and issues the second non-speculative instruction wherein a second destination register of the second non-speculative instruction is not renamed by a temporary register from the register free list and references a renamed register from the register alias table and wherein the second non-speculative instruction is issued to the execution queue when the second non-speculative instruction cannot be cancelled by the first speculative instruction;
- and
- a re-order buffer that keeps track of order of all instructions, instruction type of all instructions, the instruction type including speculative and non-speculative, and completion status of all instructions.
11 more elements
A computer program product stored on a non-transitory computer readable storage medium and including computer system instructions for causing a computer system to execute a method that is executable by a processor, the method comprising:
- issuing a first speculative instruction to a first execution queue at a first future time and issuing a second non-speculative instruction to a second execution queue upon determination that the second non-speculative instruction cannot be cancelled by the first speculative instruction;
- and
- renaming with a first register renaming unit a first destination register corresponding to the first speculative instruction and not renaming a second destination register corresponding to the second non-speculative instruction.
Dependencies are inferred from the claim text.