Back to results
US 12,566,610 B2Granted
Microprocessor with apparatus and method for replaying load instructions
AssigneeSimplex Micro, Inc.
InventorThang Minh Tran
Life of this patent
Estimating the term…
Abstract
A processor includes a time counter and a time-resource matrix and provides a method for statically dispatching load/store instructions if the required resources are available based on data stored in the time-resource matrix, and wherein execution times for the load/store instructions use a time count from the time counter to specify when the load/store instructions may be provided to a load-store unit pipeline. The execution times of the load instruction is based on the data cache hit latency time. A delay of the load/store instruction causes the load/store instruction to be replayed with known or estimated time. A load-store unit employs multiple bank queues to access multiple data banks of a data cache.
Claims20
A processor comprising:
- a time counter storing a time count representing a current time of the processor, wherein the time count is incremented periodically;
- an instruction issue unit coupled to the time counter that receives a first load/store instruction, and issues the first load/store instruction with a first preset execution time based on the time count;
- an execution queue, coupled to the time counter and the instruction issue unit, that receives the first load/store instruction from the instruction issue unit, and dispatches the first load/store instruction to a functional unit when the first preset execution time corresponds to the time count;
- dispatch logic that determines if the load/store instruction will be replayed with known or estimated delay cycles for replay;
- a register scoreboard storing a write time of a selected register from a plurality of registers in a register file, wherein the write time is a future time based on the time count;
- an instruction decode unit coupled to the register scoreboard, wherein the instruction decode unit reads a write time for each source operand of a second instruction from the register scoreboard, and uses the one or more write times to determine an execution time for the second instruction;
- and
- a time-resource matrix unit comprising a plurality of the time-resource registers for storing information relating to available resources for each time count of the N-bit time counter, the time-resource registers storing information for resources that include at least one of:
- a plurality of read buses, a plurality of write buses, and a plurality of each type of functional units, the time-resource matrix unit checking availability of resources comprising read buses, the write buses, and the functional units, for replaying a first instruction at a second preset execution time, and designating resources necessary to replay the first instruction at the second preset execution time as busy.
6 more elements
A processor comprising:
- a clock circuit;
- a time counter storing a time count representing a specific time of operation of the processor, wherein the time count is incremented by the clock circuit;
- a time-resource matrix coupled to a register scoreboard and the time counter for storing information relating to available resources for each time count of the time counter and wherein the time-resource matrix comprises busy signals of the resources based on the time count;
- an instruction issue unit coupled to the time counter for receiving a first load/store instruction, and issuing or stalling the first load/store instruction at a preset execution time as represented by the time count, based on availability of the available resources as provided by the time-resource matrix;
- an execution queue coupled to the time counter and the instruction issue unit to receive the first load/store instruction from the instruction issue unit, and dispatch the first load/store instruction to a functional unit when the preset execution time matches the time count;
- dispatch logic to track the first load/store instruction through a load-store unit pipeline and replay the first load/store instruction if the first load/store instruction cannot be completed by an expected cycle wherein the execution queue replays the load instruction by determining availability of write buses using the busy signals;
- the register scoreboard storing a write time of a register in a register file, wherein the write time is a future time specified by the time count;
- an instruction decode unit coupled to the register scoreboard, the instruction decode unit reading a write time for each source operand of a selected instruction from the register scoreboard, and using the write times corresponding to the selected instruction to determine an execution time for the selected instruction;
- and
- wherein the available resources include at least one of a plurality of read buses, a plurality of write buses, and a plurality of functional units.
7 more elements
A computer program product for issuing an instruction, the computer program product stored on a non-transitory computer readable storage medium and including instructions for causing a computer system to execute a method that is executable by a processor, the method comprising:
- issuing a load/store instruction to an execution queue or stalling execution of the load/store instruction in an instruction issue unit;
- executing the load/store instruction at a future time depending on availability of resources specified in a time-resource matrix, wherein the future time is a time defined by a time count from a periodically incremented time counter;
- replaying the load/store instruction if the load/store instruction cannot be completed at the future time;
- operating the time counter to provide a maximum time count corresponding to a latest future time to issue an instruction;
- storing a write time of a register of a register file wherein the write time is a future time defined by the time count;
- and
- storing information corresponding to available resources for each time count in the time-resource matrix, wherein the resources comprise at least one of a plurality of read buses, a plurality of write buses, and a plurality of functional units;
- wherein the time-resource matrix further comprise a busy signal for each resource based on the time count.
5 more elements
Dependencies are inferred from the claim text.