Microprocessor with apparatus and method for handling of instructions with long throughput
AssigneeSimplex Micro, Inc.
InventorThang Minh Tran
Life of this patent
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Abstract
A processor includes a time counter and a time-resource matrix and statically dispatches instructions if the resources are available based on data stored in the time-resource matrix. Execution times for the instructions use a time count from the time counter to specify when the instructions may be provided to an execution pipeline. The execution of a second instruction to a functional unit may be replayed due to the throughput time of a first instruction to the same functional unit. A busy bit and next available time of the functional unit are set when the first instruction is sent to the functional unit are the indication to replay the second instruction.
Claims19
A processor comprising:
- a time counter storing a time count representing a current time of the processor, wherein the time count is incremented periodically;
- an instruction issue unit coupled to the time counter that receives a first instruction, and issues the first instruction with a first preset execution time based on the time count;
- an execution queue coupled to the time counter and the instruction issue unit that receives the first instruction from the instruction issue unit, and dispatches the first instruction to a functional unit when the first preset execution time corresponds to the time count;
- and
- dispatch circuitry that determines if the functional unit is busy at the first preset execution time and if so then retains the first instruction in the execution queue and causes replay of the first instruction based on a next free time provided by a next free time register coupled to the dispatch circuitry.
A processor comprising:
- a clock circuit;
- a time counter storing a time count representing a specific time of operation of the processor, wherein the time count is incremented by the clock circuit;
- a time-resource matrix coupled to a register scoreboard and the time counter for storing information relating to available resources for each time count of the time counter;
- an instruction issue unit coupled to the time counter for receiving a first instruction, and issuing or stalling the first instruction at a first preset execution time, as represented by the time count, based on availability of the available resources as provided by the time-resource matrix;
- an execution queue coupled to the time counter and the instruction issue unit to receive the first instruction from the instruction issue unit, and dispatch the first instruction to a functional unit when the first preset execution time matches the time count;
- dispatch circuitry to determine if a busy bit of the functional unit is set to replay the first instruction at a new read time determined from a time count at which the functional unit is next available;
- the register scoreboard storing a write time of a register in a register file, wherein the write time is a future time specified by the time count;
- an instruction decode unit coupled to the register scoreboard, the instruction decode unit reading a write time for each source operand of a selected instruction from the register scoreboard, and using the write times corresponding to the selected instruction to determine an execution time for the selected instruction;
- and
- wherein the available resources include at least one of a plurality of read buses, a plurality of write buses, and a plurality of functional units.
A computer program product for issuing an instruction, the computer program product stored on a non-transitory computer readable storage medium and including instructions for causing a computer system to execute a method that is executable by a processor, the method comprising:
- issuing an instruction to an execution queue to execute at a preset time, wherein the preset time is a time defined by a time count from a periodically incremented time counter;
- dispatching the instruction from the execution queue to a functional unit when the preset time corresponds to the time count;
- and
- retaining the instruction in the execution queue and replaying the instruction at a next free time if a dispatch circuitry determines that the functional unit is busy at the preset time.
Dependencies are inferred from the claim text.