US 12,566,557 B2Granted

DRAM refresh control with master wordline granularity of refresh intervals

AssigneeRambus Inc.

InventorsThomas Vogelsang, Torsten Partsch, Brent Steven Haukness, John Eric Linstadt

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Abstract

DRAM cells need to be periodically refreshed to preserve the charge stored in them. The retention time is typically not the same for all DRAM cells but follows a distribution with multiple orders of magnitude difference between the retention time of cells with the highest charge loss and the cells with the lowest charge loss. Different refresh intervals are used for certain wordlines based on the required minimum retention time of the cells on those wordlines. The memory controller does not keep track of refresh addresses. After initialization of the DRAM devices, the memory controller issues a smaller number of refresh commands when compared to refreshing all wordlines at the same refresh interval.

Claims20

Dependent claims

A dynamic random access memory (DRAM) device, comprising:

a command interface to receive a refresh command;
circuitry to determine, in response to the refresh command, whether to perform a selected one of a first type of refresh operation and a second type of refresh operation;
a plurality of indicator bits each associated with a respective one of a plurality of groups of wordlines that are activated during refresh operations, each of the plurality of groups of wordlines comprising a plurality of wordlines;
to maintain data retention, during a span of a selected number of refresh periods:
the command interface to receive a total number of the refresh command;
the DRAM to perform a first number of the first type of refresh operation;
the DRAM to perform a second number of the second type of refresh operation;
the second number based on a third number of the plurality of indicator bits that are set to a first value, the second number to be less than the first number;
and,
wordline address generation circuitry to progressively select respective ones of the plurality of groups of wordlines, in response to the first type of refresh operation and in a first internally generated sequence, and to progressively select, in response to the second type of refresh operation and in a second internally generated sequence, respective ones of the plurality of groups of wordlines associated with respective indicator bits being set to the first value.

7 more elements

A dynamic random access memory (DRAM) device, comprising:

a plurality of master wordline refresh interval flags each associated with a respective one of a plurality of master wordlines that are activated during refresh operations;
a command interface to receive at least a refresh command;
circuitry to, in response to the refresh command, treat the refresh command as a one of a first type of refresh command or a second type of refresh command, the first type of refresh command to be used to activate all of the plurality of master wordlines thereby refreshing all rows of a bank, the second type of refresh command to be used to activate a subset of the master wordlines thereby refreshing a corresponding subset of rows of the bank, the subset to be determined by values of the plurality of master wordline refresh interval flags;
first refresh cycle interval address generation circuitry to, in response to a first plurality of the refresh commands treated as the first type of refresh command that are received over a first time interval, generate first refresh cycle interval addresses to refresh all rows of the bank;
and,
second refresh cycle interval address generation circuitry to, in response to a second plurality of refresh commands treated as the second type of refresh command that are received over the first time interval, generate second refresh cycle interval addresses to refresh a subset of rows of the bank.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/569,518Filed 21 Jun 2022 · us provisional application
Priority: 30 Jun 2021
Published: US 2024/0281154 A122 Aug 2024
Granted: 3 Mar 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

G06F 3/0625
Specifically adapted to achieve a particular effect: power saving in storage systems
G06F 3/0659
Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices: command handling…
G06F 3/0673
In-line storage system: single storage device
G11C 8/14
Arrangements for selecting an address in a digital store: word line organisation; Word line lay-out