Power via with reduced resistance

A method comprising:

• forming a first micro through silicon via (TSV) at a first location on a surface of a silicon substrate layer, wherein the first micro TSV traverses through the silicon substrate layer to physically connect to a backside metal layer;
• forming a second micro TSV at a second location different from the first location on the surface of the silicon substrate layer;
• and
• forming a first power rail physically abutting each of the first micro TSV and the second micro TSV.

A computing system comprising:

• a memory configured to store instructions of one or more tasks and source data to be processed by the one or more tasks;
• an integrated circuit configured to execute the instructions using the source data, wherein the integrated circuit comprises:
• a first micro through silicon via (TSV) at a first location on a surface of a silicon substrate layer, wherein the first micro TSV traverses through the silicon substrate layer to physically connect to a backside metal layer;
• a second micro TSV at a second location different from the first location on the surface of the silicon substrate layer;
• and
• a first power rail physically abutting each of the first micro TSV and the second micro TSV;
• and
• wherein responsive to a potential being applied to an input node of a cell of the integrated circuit, a current is conveyed from the input node to an output node of the cell through at least the first power rail.