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US 12,563,806 B2Granted
Method for forming a low-k spacer
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHsiu-Yu Kang, Hong-Wei Chen
Life of this patent
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Abstract
The present disclosure is directed to formation of a low-k spacer. For example, the present disclosure includes an exemplary method of forming the low-k spacer. The method includes depositing the low-k spacer and subsequently treating the low-k spacer with a plasma and/or a thermal anneal. The low-k spacer can be deposited on a structure protruding from the substrate. The plasma and/or thermal anneal treatment on the low-k spacer can reduce the etch rates of the spacer so that the spacer is etched less in subsequent etching or cleaning processes.
Claims20
A semiconductor device, comprising:
- a gate stack, disposed on a substrate, comprising a high-k gate dielectric layer, a metal gate electrode, and an insulating layer;
- an oxide layer disposed directly on sidewalls of the high-k gate dielectric layer, the metal gate electrode, and the insulating layer, wherein a top surface of the oxide layer is coplanar with a top surface of the insulating layer;
- a first spacer, disposed along the sidewall surface of the gate stack, comprising a first dielectric material with a first dielectric constant;
- a second spacer, disposed on the first spacer, comprising a second dielectric material with a second dielectric constant lower than the first dielectric constant, wherein the top surface of the oxide layer is coplanar with a top surface of the first spacer and is non-coplanar with a top surface of the second spacer;
- and
- a source/drain region disposed on the substrate, wherein the first spacer is non-overlapping with the source/drain region.
3 more elements
A semiconductor device, comprising:
- a gate stack, disposed on a substrate, comprising:
- a high-k gate dielectric layer;
- a metal gate electrode on the high-k gate dielectric layer;
- an insulating layer on the metal gate electrode;
- and
- an oxide layer in contact with sidewalls of the high-k gate dielectric layer, the metal gate electrode, and the insulating layer, wherein a top surface of the oxide layer is coplanar with a top surface of the gate stack;
- a first spacer on a sidewall surface of the oxide layer and comprising a first dielectric constant, wherein a top surface of the first spacer is coplanar with a top surface of the oxide layer;
- a second spacer comprising silicon oxycarbide and formed on a sidewall surface of the first spacer, wherein the second spacer comprises a second dielectric constant lower than the first dielectric constant, and wherein a top surface of the second spacer is non-coplanar with top surfaces of the oxide layer and the first spacer;
- and
- a source/drain region disposed on the substrate, wherein the first spacer is non-overlapping with the source/drain region.
7 more elements
A semiconductor device, comprising:
- a gate stack, disposed on a substrate, comprising a high-k gate dielectric layer, a metal gate electrode, and an insulating layer;
- an oxide layer disposed directly on sidewalls of the high-k gate dielectric layer, the metal gate electrode, and the insulating layer, wherein a top surface of the oxide layer is coplanar with a top surface of the insulating layer;
- a first spacer, disposed on the oxide layer, comprising:
- a first silicon atomic concentration,
- a first carbon atomic concentration, and
- a first oxygen atomic concentration;
- a second spacer, in contact with a sidewall of the first spacer, comprising:
- a second silicon atomic concentration lower than the first atomic concentration;
- a second carbon atomic concentration higher than the first carbon atomic concentration;
- and
- a second oxygen atomic concentration higher than the first oxygen atomic concentration, wherein the top surface of the oxide layer is coplanar with a top surface of the first spacer and is non-coplanar with a top surface of the second spacer;
- and
- a source/drain region disposed on the substrate, wherein the first spacer is non-overlapping with the source/drain region.
10 more elements
Dependencies are inferred from the claim text.