Semiconductor device and method of fabricating the same

A semiconductor device, comprising:

• a substrate;
• an interconnection layer disposed on the substrate, wherein the interconnection layer comprises a plurality of dielectric layers and a plurality of conductive layers alternately stacked up along a build-up direction;
• a transistor array located in between the plurality of dielectric layers of the interconnection layer and electrically connected to the plurality of conductive layers, wherein the transistor array comprises:
• a first transistor comprising a gate electrode, a gate dielectric, a channel layer and source and drain electrodes sequentially disposed over the substrate along the build-up direction;
• a dummy transistor comprising a dummy gate electrode, a dummy gate dielectric and a dummy channel layer sequentially disposed over the substrate along the build-up direction;
• and
• a protection structure encircling the first transistor and the dummy transistor, wherein a lateral dimension of the protection structure increases along the build-up direction.

A method of fabricating a semiconductor device, comprising:

• forming a first transistor over a substrate, which comprises:
• forming a gate electrode over the substrate;
• forming a gate dielectric disposed on the gate electrode;
• and
• forming a channel layer disposed on the gate dielectric;
• patterning the gate electrode, the gate dielectric and the channel layer to form trenches penetrating through the gate electrode, the gate dielectric and the channel layer;
• forming a protection structure in the trenches to laterally surround the gate electrode, the gate dielectric and the channel layer of the first transistor, wherein forming the protection structure comprises:
• forming a first capping layer in the trenches to laterally surround and contact the gate electrode, the gate dielectric and the channel layer of the first transistor;
• conformally forming a second capping layer over the first capping layer and in the trenches;
• and
• forming a dielectric portion on the first capping layer and over the second capping layer to fill up the trenches and to laterally surround the first transistor.