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US 12,563,754 B2Granted
Hybrid decoupling capacitor and method forming same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHao-Chieh Chan, Chung-Hui Chen
Life of this patent
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Abstract
A device includes a first capacitor and a second capacitor connected to the first capacitor in parallel. The first capacitor includes a semiconductor region and a first plurality of gate stacks. The first plurality of gate stacks comprise a plurality of gate dielectrics over and contacting the semiconductor region, and a plurality of gate electrodes over the plurality of gate dielectrics. The second capacitor includes an isolation region, a second plurality of gate stacks over the isolation region, and a plurality of conductive strips over the isolation region and parallel to the second plurality of gate stacks. The second plurality of gate stacks and the plurality of conductive strips are laid out alternatingly.
Claims20
A device comprising:
- a power supply node and an electrical ground;
- a semiconductor substrate;
- a first dielectric isolation region extending into the semiconductor substrate;
- a capacitor coupled between the power supply node and the electrical ground, wherein the capacitor comprises:
- a protruding semiconductor region encircled by, and protruding higher than, the first dielectric isolation region, wherein the protruding semiconductor region comprises:
- a first sidewall and a second sidewall parallel to each other;
- and
- a third sidewall and a fourth sidewall parallel to each other, and perpendicular to the first sidewall and the second sidewall;
- a first plurality of gate stacks contacting a top surface and the first sidewall and the second sidewall of the protruding semiconductor region, wherein a gate stack in the first plurality of gate stacks overlaps a portion of the protruding semiconductor region to have an overlap region in a top view of the device, and wherein in the top view, the overlap region has a length in a lengthwise direction parallel to the third sidewall, and a width in a widthwise direction parallel to the first sidewall, and wherein the length is greater than the width, and wherein the first plurality of gate stacks are electrically interconnected;
- and
- a plurality of contact plugs electrically interconnected, wherein the first plurality of gate stacks and the plurality of contact plugs are laid out alternatingly;
- and
- a dielectric layer, wherein both of the first plurality of gate stacks and the plurality of contact plugs comprise portions in the dielectric layer.
10 more elements
A device comprising:
- a power supply node and an electrical ground;
- a semiconductor substrate;
- a Shallow Trench Isolation (STI) region extending into the semiconductor substrate, wherein the STI region comprises:
- a first plurality of portions, wherein the first plurality of portions encircle a plurality of semiconductor regions of the semiconductor substrate;
- and
- a second plurality of portions, wherein the first plurality of portions and the second plurality of portions are portions of the STI region that is continuous;
- a plurality of varactors, each formed with one of the plurality of semiconductor regions acting as a first capacitor plate, wherein each of the plurality of varactors comprises:
- a first plurality of elongate gate electrodes acting as second capacitor plates of the plurality of varactors, each extending on a top surface and opposing sidewalls of one of the plurality of semiconductor regions, wherein in a top view of the device, each of the first plurality of elongated gate electrodes overlaps the one of the plurality of semiconductor regions to form an overlap region, and wherein a lengthwise direction of the overlap region is perpendicular to the opposing sidewalls;
- and
- a plurality of contact plugs, each between two neighboring ones of the first plurality of elongated gate electrodes, wherein the plurality of contact plugs are electrically connected to the plurality of semiconductor regions, wherein the plurality of varactors are connected in parallel as a capacitor, and wherein the capacitor is coupled between the power supply node and the electrical ground;
- and
- an inter-layer dielectric, wherein the first plurality of elongate gate electrodes and the plurality of contact plugs comprise portions in the inter-layer dielectric.
9 more elements
A device comprising:
- a power supply node and an electrical ground;
- a semiconductor substrate;
- a dielectric isolation region extending into the semiconductor substrate, wherein the semiconductor substrate comprises a protruding semiconductor fin protruding higher than and encircled by the dielectric isolation region;
- and
- a capacitor coupled between the power supply node and the electrical ground, the capacitor comprising:
- a plurality elongate gate electrodes, with each of the plurality of elongate gate electrodes extending on the protruding semiconductor fin;
- a plurality of elongated silicide regions at surfaces of the protruding semiconductor fin;
- and
- a plurality of elongated contact plugs over and contacting the plurality of elongated silicide regions, wherein the plurality of elongate gate electrodes and the plurality of elongated contact plugs are alternatingly situated, and wherein lengthwise directions of the plurality of elongate gate electrodes and the plurality of elongated contact plugs are parallel to each other.
6 more elements
Dependencies are inferred from the claim text.