Vertical field effect transistors and methods for forming the same

A semiconductor structure comprising:

• a two-dimensional array of vertical stacks located over a substrate, wherein each of the two-dimensional array of vertical stacks includes, from bottom to top, a bottom electrode, a dielectric pillar, and a top electrode of which all sidewalls are vertically coincident with all sidewalls of the dielectric pillar;
• active layers comprising a semiconducting metal oxide material and extending over sidewalls of a respective one of vertical stacks;
• gate stacks overlying a respective row of the active layers, wherein each of the gate stacks comprises a row of gate dielectrics arranged along a first horizontal direction and a gate electrode;
• and
• a dielectric wall structure laterally surrounding each of the gate stacks and providing electrical isolation between each adjacent pair of gate electrodes among the gate electrodes, wherein each sidewall of the dielectric wall structure comprises vertically straight and laterally concave surface segments that are equidistant from a most proximal sidewall among sidewalls of a respective row of top electrodes that are arranged along the first horizontal direction, wherein:
• each of the active layers comprises a top edge that is located above a horizontal plane including top surfaces of the top electrodes of the two-dimensional array of vertical stacks;
• and
• each of the active layers comprises a bottommost surface that is located below an additional horizontal plane including bottom surfaces of the bottom electrodes of the two-dimensional array of vertical stacks.

A semiconductor structure comprising:

• a two-dimensional array of vertical stacks located over a substrate, wherein each of the two-dimensional array of vertical stacks includes, from bottom to top, a bottom electrode, a dielectric pillar, and a top electrode of which all sidewalls are vertically coincident with all sidewalls of the dielectric pillar;
• active layers comprising a semiconducting metal oxide material, extending over sidewalls of a respective row of vertical stacks that are arranged along a first horizontal direction, and laterally spaced apart along a second horizontal direction;
• gate stacks overlying a respective one of the active layers, wherein each of the gate stacks comprises a gate dielectric and a gate electrode;
• and
• dielectric wall structures interlaced with the gate stacks along the second horizontal direction, wherein the dielectric wall structures vertically extend from a first horizontal plane including top surfaces of the gate electrodes at least to a second horizontal plane including bottom surfaces of the bottom electrodes, wherein:
• each of the active layers comprises a top edge that is located above a horizontal plane including top surfaces of the top electrodes of the two-dimensional array of vertical stacks;
• and
• each of the active layers comprises a bottommost surface that is located below an additional horizontal plane including bottom surfaces of the bottom electrodes of the two-dimensional array of vertical stacks.