Semiconductor devices

A semiconductor device comprising:

• a substrate including an active region extending in a first direction;
• a gate electrode on the substrate, the gate electrode extending in a second direction and intersecting the active region;
• a first channel layer, a second channel layer, and a third channel layer spaced apart from each other in a third direction, the third direction perpendicular to an upper surface of the substrate, wherein the first channel layer, the second channel layer and the third channel layer are sequentially stacked on the active region, and wherein the first channel layer, the second channel layer and the third channel layer are surrounded by the gate electrode;
• a first dielectric layer surrounding the first channel layer, a second dielectric layer surrounding the second channel layer, and a third dielectric layer surrounding the third channel layer, wherein the first dielectric layer, the second dielectric layer and the third dielectric layer are sequentially stacked in the third direction on the active region, wherein the first dielectric layer, the second dielectric layer and the third dielectric layer include at least one of a ferroelectric material or an anti-ferroelectric material, and wherein each of the first dielectric layer, the second dielectric layer and the third dielectric layer has a different thickness;
• and
• source/drain regions in recess regions in which the active region is recessed, the source/drain regions on both sides of the gate electrode, and the source/drain regions in contact with the first channel layer, the second channel layer and the third channel layer.

A semiconductor device comprising:

• a memory cell array including a plurality of memory elements;
• and
• a peripheral circuit region including peripheral circuits configured to control the memory cell array,
• wherein each of the plurality of memory elements includes
• an active region extending in a first direction,
• a gate electrode intersecting the active region, the gate electrode extending in a second direction,
• a plurality of channel layers on the active region, the plurality of channel layers spaced apart from each other in a third direction, the third direction perpendicular to an upper surface of the active region, and the plurality of channel layers surrounded by the gate electrode, and
• a plurality of dielectric layers between the plurality of channel layers and the gate electrode, the plurality of dielectric layers including at least one of a ferroelectric material or an anti-ferroelectric material, and
• wherein in each of the plurality of memory elements, a number of the plurality of channel layers is N, where N is a natural number equal to or greater than 2, and each of the plurality of memory elements is configured to store N bits of data or less.