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US 12,562,941 B2Granted
Joint timing recovery and decision feedback equalizer adaptation in wireline network receivers
AssigneeTexas Instruments Incorporated
InventorsSaravanakkumar Radhakrishnan, Raghu Ganesan
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Abstract
A network communications receiver and a method of operating the same in symbol timing recovery and equalization adaptation. A data converter samples a received analog signal at an initialization frequency higher than the symbol frequency of the received signal, and converts the samples to a digital sample stream. A decision feedback equalizer including a digital filter with one or more tap weights is adapted, and an error measurement obtained from the output of the decision feedback equalizer. In response to the error measurement crossing an error threshold value, a timing loop including timing error detection is initiated to adjust the phase of the sampling clock applied to the data converter.
Claims23
A method comprising:
- sampling an input analog signal having a symbol frequency responsive to a sampling clock;
- converting the sampled input analog signal to a digital sample stream;
- equalizing the digital sample stream with a decision feedback equalizer to produce an output sample stream;
- calculating an error measurement from a plurality of samples of the output sample stream;
- identifying a minimum of the error measurement over the plurality of samples;
- calculating an error threshold value relative to the identified minimum of the error measurement;
- and
- responsive to the error measurement crossing the error threshold value, adjusting a phase of the sampling clock.
5 more elements
A method comprising:
- sampling an input analog signal having a symbol frequency responsive to a sampling clock;
- converting the sampled input analog signal to a digital sample stream;
- equalizing the digital sample stream with a decision feedback equalizer to produce an output digital stream;
- calculating a mean squared error for each of a plurality of samples of the output sample stream;
- observing a periodicity of the mean squared error over the plurality of samples;
- and
- responsive to the error measurement crossing an error threshold value:
- calculating a frequency offset corresponding to the observed periodicity of minima;
- and
- adjusting a phase of the sampling clock according to the frequency offset.
7 more elements
A network communications receiver comprising:
- a data converter adapted to receive an analog signal at an input and output a digital sample stream at an output, the analog signal having a symbol frequency, the data converter configured to sample the analog signal responsive to a sampling clock signal and convert the sampled signal to the digital sample stream;
- clock generation circuitry configured to generate the sampling clock signal at a phase and frequency responsive to a clock control signal, the clock generation circuitry coupled to the data converter;
- digital receiver circuitry having an input coupled to the output of the data converter to receive the digital sample stream, and comprising:
- a decision feedback equalizer (DFE) comprising a digital filter with one or more tap weights, and configured to produce an output digital stream from the digital sample stream;
- error measurement circuitry coupled to the DFE and configured to:
- measure error in samples of the output digital stream;
- identify a periodicity of the measured error over a plurality of samples of the output sample stream;
- and
- calculate a frequency offset corresponding to the identified periodicity of the measured error:
- clock control circuitry coupled to the DFE and configured to generate the clock control signal based on the frequency offset;
- sequencer logic coupled to the DFE, the error measurement circuitry, and the clock control circuitry, the sequencer logic configured to control the operation of the decision feedback equalizer, the error measurement circuitry, and the clock control circuitry according to a plurality of operations comprising:
- generating a clock control signal responsive to an initialization frequency signal corresponding to a frequency above the symbol frequency of the received analog signal;
- adapting at least one of the tap weights of the DFE;
- calculating an error measurement from the output sample stream;
- and
- responsive to the error measurement crossing an error threshold value, adjusting the clock control signal.
13 more elements
A network communications receiver comprising:
- a data converter adapted to receive an analog signal at an input and output a digital sample stream at an output, the analog signal having a symbol frequency, the data converter configured to sample the analog signal responsive to a sampling clock signal and convert the sampled signal to the digital sample stream;
- clock generation circuitry configured to generate the sampling clock signal at a phase and frequency responsive to a clock control signal, the clock generation circuitry coupled to the data converter;
- digital receiver circuitry having an input coupled to the output of the data converter to receive the digital sample stream, and comprising:
- a decision feedback equalizer (DFE) comprising a digital filter with one or more tap weights, and configured to produce an output digital stream from the digital sample stream;
- timing error detection circuitry configured to calculate a timing error signal from the output digital stream;
- error measurement circuitry coupled to the DFE and configured to:
- calculate a mean squared error in samples of the output sample stream, and
- identify a minimum of the mean squared error over a plurality of samples of the output sample stream;
- clock control circuitry coupled to the DFE and configured to generate the clock control signal;
- sequencer logic coupled to the DFE, the error measurement circuitry, and the clock control circuitry, and configured to generate a start signal to the timing error detection circuitry responsive to the error measurement being below an error threshold value determined from the minimum of the mean squared error.
7 more elements
A physical layer transceiver comprising:
- a media independent interface;
- a media dependent interface;
- a transmit processing block coupled to the media independent interface;
- a transmitter subsystem, coupled between the transmit processing block and the media dependent interface, the transmitter subsystem configured to communicate analog signals corresponding to data from the transmit processing block over the media dependent interface;
- a data converter coupled to the media dependent interface and adapted to receive an analog signal from the media dependent interface, the analog signal having a symbol frequency, the data converter configured to sample the analog signal responsive to a sampling clock signal and convert the sampled signal to a digital sample stream;
- clock generation circuitry coupled to the data converter and configured to generate the sampling clock signal at a phase and frequency responsive to a clock control signal;
- and
- a receive processing block coupled to the media independent interface, and comprising:
- symbol timing recovery and equalization circuitry, comprising:
- a decision feedback equalizer comprising a digital filter with one or more tap weights, and configured to produce an output digital stream from the digital sample stream;
- error measurement circuitry coupled to the decision feedback equalizer and configured to measure error in samples of the output digital stream;
- clock control circuitry coupled to the error measurement circuitry and configured to generate the clock control signal;
- and
- sequencer logic coupled to the decision feedback equalizer, the error measurement circuitry, and clock control circuitry, the sequencer logic configured to control the operation of the decision feedback equalizer, the error measurement circuitry, and the clock control circuitry according to a plurality of operations comprising:
- generating a clock control signal responsive to an initialization frequency signal corresponding to a frequency above the symbol frequency of the received analog signal;
- adapting at least one of the tap weights of the DFE;
- calculating an error measurement from the output sample stream;
- and
- responsive to the error measurement crossing an error threshold value, adjusting the clock control signal, wherein the error measurement circuitry is configured to:
- calculate a mean squared error in samples of the output sample stream, and
- identify a minimum of the mean squared error over a plurality of samples of the output sample stream;
- and wherein the sequencer logic is further configured to generate a start signal to a timing error detection circuitry responsive to the error measurement being below an error threshold value determined from the minimum of the mean squared error.
19 more elements
A physical layer transceiver comprising:
- a media independent interface;
- a media dependent interface;
- a transmit processing block coupled to the media independent interface;
- a transmitter subsystem, coupled between the transmit processing block and the media dependent interface, the transmitter subsystem configured to communicate analog signals corresponding to data from the transmit processing block over the media dependent interface;
- a data converter coupled to the media dependent interface and adapted to receive an analog signal from the media dependent interface, the analog signal having a symbol frequency, the data converter configured to sample the analog signal responsive to a sampling clock signal and convert the sampled signal to a digital sample stream;
- clock generation circuitry coupled to the data converter and configured to generate the sampling clock signal at a phase and frequency responsive to a clock control signal;
- and
- a receive processing block coupled to the media independent interface, and comprising:
- symbol timing recovery and equalization circuitry, comprising:
- a decision feedback equalizer comprising a digital filter with one or more tap weights, and configured to produce an output digital stream from the digital sample stream;
- error measurement circuitry coupled to the decision feedback equalizer and configured to measure error in samples of the output digital stream;
- clock control circuitry coupled to the error measurement circuitry and configured to generate the clock control signal;
- and
- sequencer logic coupled to the decision feedback equalizer, the error measurement circuitry, and clock control circuitry, the sequencer logic configured to control the operation of the decision feedback equalizer, the error measurement circuitry, and the clock control circuitry according to a plurality of operations comprising:
- generating a clock control signal responsive to an initialization frequency signal corresponding to a frequency above the symbol frequency of the received analog signal;
- adapting at least one of the tap weights of the DFE;
- calculating an error measurement from the output sample stream;
- and
- responsive to the error measurement crossing an error threshold value, adjusting the clock control signal, wherein the error measurement circuitry is configured to:
- calculate a mean squared error in samples of the output sample stream;
- identify a periodicity of the mean squared error over a plurality of samples of the output sample stream;
- and
- calculate a frequency offset corresponding to the identified periodicity of mean squared error;
- wherein the clock control circuitry is configured to adjust the clock control signal responsive to the frequency offset.
21 more elements
Dependencies are inferred from the claim text.