Systems and methods for interference cancellation
AssigneeAvago Technologies International Sales Pte. Limited
InventorsYonghyun Shim, Guansheng Li, Delong Cui, Jun Cao
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AssigneeAvago Technologies International Sales Pte. Limited
InventorsYonghyun Shim, Guansheng Li, Delong Cui, Jun Cao
Estimating the term…
An apparatus for canceling clock-to-signal interference in a multi-lane SerDes comprising an analog front-end circuit receiving an input signal from a signal path mixed with interference from a clock path. The apparatus includes a phase interpolator circuit implemented in the clock path to generate multiple phases of a clock signal and to provide a timing rotated by the phases for a track-and-hold circuit to sample the input signal and the interference in every cycle. The apparatus also includes an analog-to-digital converter configured to digitize the input signal and the interference to provide an ADC output and a digital-interference-cancellation circuit configured to demultiplex the ADC output and detect a baseline offset associated with the interference sampled at one of the phases in each demultiplexed path using a digital loop to calibrate the baseline offset.
An apparatus comprising:
An apparatus comprising:
A method comprising:
Dependencies are inferred from the claim text.