Analog-to-digital circuit and operation method thereof

An image sensor comprising:

• a pixel array including a plurality of pixel columns respectively generating a plurality of pixel signals;
• and
• an analog-to-digital converter (ADC) circuit including a ramp generator configured to generate a ramp signal based on a system clock signal, a clock generator configured to generate first to Nth clock signals based on the system clock signal, and a plurality of ADCs,
• wherein a first ADC among the plurality of ADCs includes:
• a first comparator configured to generate a first comparison signal based on a result of comparing a first pixel signal from a first pixel column among the plurality of pixel columns and the ramp signal from the ramp generator;
• a first additional latch circuit configured to generate a first additional binary signal based on the system clock signal and the first comparison signal;
• and
• first to N-th latch circuits configured to generate first to N-th latch signals based on the first comparison signal and corresponding clock signal among the first to Nth clock signals, wherein “N” is a positive integer.

An operation method of an analog-to-digital converter (ADC) circuit which includes a ramp generator, a clock generator, a comparator, and a counter, the method comprising:

• generating, by the ramp generator, a ramp signal based on a system clock signal;
• generating, by the clock generator, first to Nth clock signals based on the system clock signal;
• generating, by the comparator, a comparison signal based on a result of comparing a pixel signal received from a pixel array and the ramp signal;
• and
• generating, by the counter, an additional binary signal and first to N-th latch signals based on the comparison signal, the system clock signal, and the first to Nth clock signals,
• wherein the counter includes:
• an additional latch circuit configured to generate the additional binary signal based on the system clock signal and the comparison signal;
• and
• first to N-th latch circuits configured to generate, respectively, the first to N-th latch signals based on the comparison signal and corresponding clock signal among the first to Nth clock, and
• wherein “N” is a positive integer.