Filter with low leakage power-down switches
AssigneeInfineon Technologies AG
InventorsPeter Unterkircher, Ralf-Rainer Schledz
Life of this patent
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Abstract
A circuit includes: a low-pass filter that includes a resistor coupled between a first node and a second node, and a capacitor coupled between the second node and a reference node. The circuit further includes: a first transistor, where a drain terminal of the first transistor is coupled to the second node, and a source terminal of the first transistor is coupled to the first node; and a second transistor, where a drain terminal of the second transistor is coupled to the first node, and a source terminal of the second transistor is coupled to the reference node, where a gate terminal of the first transistor and a gate terminal of the second transistor are coupled to a control node.
Claims20
A circuit comprising:
- a low-pass filter comprising:
- a resistor coupled between a first node and a second node;
- and
- a capacitor coupled between the second node and a reference node;
- a first transistor, wherein a drain terminal of the first transistor is coupled to the second node, and a source terminal of the first transistor is coupled to the first node;
- and
- a second transistor, wherein a drain terminal of the second transistor is coupled to the first node, and a source terminal of the second transistor is coupled to the reference node, wherein a gate terminal of the first transistor and a gate terminal of the second transistor are coupled to a control node.
A circuit comprising:
- a low-pass filter comprising a resistor and a capacitor, wherein the resistor is coupled between a first node and a second node, and the capacitor is coupled between the second node and a reference node;
- and
- a power-down circuit comprising a first transistor and a second transistor coupled in series between the second node and the reference node, wherein a drain terminal of the first transistor is coupled to the second node, wherein a source terminal of the first transistor is coupled to the first node and coupled to a drain terminal of the second transistor, wherein a source terminal of the second transistor is coupled to the reference node, wherein a gate terminal of the first transistor and a gate terminal of the second transistor are coupled to an input terminal of the power-down circuit.
Dependencies are inferred from the claim text.