Charge pump circuits and methods for operating the same

A circuit, comprising:

• a first charge capacitor having a first terminal and a second terminal coupled to a first clock signal and a first common node, respectively, wherein the first common node is coupled between a first transistor and a second transistor;
• a second charge capacitor having a first terminal and a second terminal coupled to a second clock signal and a second common node, respectively, wherein the second clock signal is logically inverse to the first clock signal, wherein the second common node is coupled between a third transistor and a fourth transistor;
• a fifth transistor having a gate terminal, a source terminal, and a drain terminal that are connected to the first common node, a gate terminal of the second transistor, and the second common node, respectively, wherein the fifth transistor and the second transistor both have a first conductive type;
• and
• a sixth transistor having a gate terminal, a source terminal, and a drain terminal that are connected to the second common node, a gate terminal of the fourth transistor, and the first common node, respectively, wherein the sixth transistor and the fourth transistor both have the first conductive type;
• wherein both of the second and third transistors are configured to be activated alternately with respect to both of the first and fourth transistors so as to boost an output voltage as a multiply of an input voltage.

A method for operating a charge pump circuit, comprising:

• providing a charge pump circuit including first, second, third, and fourth transistors, and first and second charge capacitors, wherein the first and second transistors are coupled in series to each other at a first node and the third and fourth transistors are coupled in series to each other at a second node, and wherein the first node is coupled to a first clock signal through a first charge capacitor and the second node is coupled to a second clock signal through a second charge capacitor, the second clock signal being logically inverse to the first clock signal;
• charging, during a first phase, the first node and the second node to a first multiply of a supply voltage and to the supply voltage, respectively, through activating the second and third transistors and deactivating the first and fourth transistors;
• and
• charging, during a second phase, the first node and the second node to the supply voltage and a second multiply of the supply voltage, respectively, through activating the first and fourth transistors and deactivating the second and third transistors;
• wherein, during the first phase, the first node is isolated from a gate terminal of the third transistor by deactivating at least a fifth transistor, and wherein, during the second phase, the first node is isolated from a gate terminal of the fourth transistor by deactivating at least a sixth transistor.