Independently-addressable high power surface-emitting laser array with tight-pitch packing

A semiconductor surface-emitting laser array, comprising:

• a plurality of independently addressable pixels arranged in an interdigitated linear array on a common substrate chip and including a dedicated channel associated with an address trace line for each pixel, wherein the interdigitated linear array is configured in a tight pitch arrangement;
• at least one laser aperture associated with each independently addressable pixel, wherein each of the at least one aperture is configured to fit within a pitch of each address trace line associated with each channel for each of the plurality of independently addressable pixels, wherein the squeezed of the shape is along a direction of the linear array to fit within available space of the pitch or the elongated is in a direction of an address line;
• an electrical contact pad associated with each address trace line for each independently addressable pixel, wherein each electrical contact pad is configured to accept wire bonding;
• wherein the plurality of independently addressable pixels is arranged along at least two rows with one set of address lines coming in from a top of the common substrate chip and are connecting to a first row of independently addressable pixels and another set of address lines coming in from the bottom of the common substrate chip and are connected to a second row of independently addressable pixels;
• and
• a submount with a built-in heat sink for dissipating heat generated by the semiconductor surface-emitting laser array, the submount comprising a three-dimensional mechanical body, the submount comprising integrated slots dimensioned and positioned to receive driver chips or electrical interposers for electrical connection to cathode and anode contacts of the semiconductor surface-emitting laser array, wherein the submount comprises mounting holes for alignment and attachment of optical elements comprising optics mounts and wherein the submount is configured to support and align the semiconductor surface-emitting laser array, the driver chips or electrical interposers, and the optical elements in a mechanically integrated and thermally managed structure aligned with the each address trace line.