Testing method and testing system

Abstract

Disclosed are a testing method and a testing system. The testing method is configured to scan a three-dimensional memory chip. The three-dimensional memory chip includes a plurality of memory chips stacked with each other. The testing method includes: dividing each memory chip into a plurality of memory blocks; testing each memory block to detect a total failed first signal line quantity from a plurality of first signal lines extending along a first direction in each memory block, and to detect a total failed memory cell quantity of each memory block; and determining a failed bit quantity threshold according to the total failed first signal line quantity, and comparing the total failed memory cell quantity with the failed bit quantity threshold, to accordingly determine whether to set a marked first signal line quantity.

Dependencies are inferred from the claim text.