Non-volatile memory with concurrent programming

A method, comprising:

• concurrently applying programming to non-volatile memory cells in multiple regions of a non-volatile memory structure, the concurrently applying programming to non-volatile memory cells in multiple regions comprises turning on select lines for all regions of the multiple regions of the non-volatile memory structure and applying doses of a programming voltage concurrently to the non- volatile memory cells in the multiple regions of the non-volatile memory structure;
• performing program verify for the programming in only one region of the multiple regions of the non-volatile memory structure without performing program verify for the programming in other regions of the multiple regions of the non-volatile memory structure, the performing program verify for the programming in only one region of the multiple regions of the non-volatile memory structure comprises turning on a select line for the one region of the multiple regions of the non-volatile memory structure while turning off select lines for other regions of the multiple regions of the non- volatile memory structure;
• and
• completing the programming for all of the multiple regions being concurrently programmed in response to successful program verify for the programming in the one region of the multiple regions.

A non-volatile storage apparatus, comprising:

• a three dimensional non-volatile memory structure comprising non-volatile memory cells, the non-volatile memory structure includes multiple blocks of non-volatile memory cells, each block of the multiple blocks is divided into multiple regions, each region of the of the multiple blocks includes a plurality of non-volatile memory cells;
• a set of word lines connected the non-volatile memory structure;
• a plurality of bit lines, each bit line of the plurality of bit lines is connected to all of the multiple regions of the multiple blocks;
• a set of select lines, each select line of the set of select lines is connected to and controls a different region of the multiple regions of the multiple blocks, each region of the multiple regions of the multiple blocks is controlled by a different select line of the set of select lines;
• and
• a control circuit connected to the set of word lines as well as the set of select lines and the plurality of bit lines, the control circuit is configured to concurrently program memory cells in each region of the multiple regions of each block of the multiple blocks.