Multiple independent on-chip interconnect

A system comprising:

• an integrated circuit implementing a system-on-a-chip (SOC), wherein the SOC includes:
• a plurality of processor clusters, wherein a given processor cluster comprises two or more central processing unit (CPU) circuits coupled to a given last level cache;
• a plurality of peripheral circuits including at least one interface circuit configured to communicate with devices external to the SOC;
• a plurality of graphics processing unit (GPU) circuits;
• a plurality of memory controllers configured to communicate with a system memory;
• and
• a plurality of network switches including:
• a first subset of network switches interconnected to form a CPU network coupled between the plurality of processor clusters and the plurality of memory controllers, wherein the plurality of memory controllers are directly coupled to the CPU network, and wherein the given processor cluster of the plurality of processor clusters is configured to communicate with the system memory via the CPU network;
• and
• a second subset of network switches configured to form an input/output (I/O) network coupled between the plurality of peripheral circuits and the plurality of memory controllers, wherein the plurality of memory controllers are directly coupled to the I/O network, and wherein a given peripheral circuit of the plurality of peripheral circuits is configured to communicate with the system memory via the I/O network;
• and
• a third subset of network switches interconnected to form a GPU network coupled between the plurality of memory controllers and the plurality of GPU circuits, wherein the plurality of memory controllers are directly coupled to the GPU network, and wherein a given GPU circuit of the plurality of GPU circuits is configured to communicate with the system memory via the GPU network;
• wherein the CPU network, the GPU network and the I/O network are logically and physically independent from one another.

A method comprising:

• a memory controller communicating with a system memory;
• communicating with the system memory, via the memory controller and a first network having a first plurality of network switches, using a plurality of processor clusters of an electronic circuit, wherein a given processor cluster of the plurality of processor clusters includes two or more central processing unit (CPU) circuits coupled to a given last level cache and wherein the memory controller is directly coupled to the first network;
• and
• communicating with the system memory, via the memory controller and a second network having a second plurality of network switches, using a plurality of graphics processing unit (GPU) circuits of the electronic circuit, wherein the memory controller is directly coupled to the second network and wherein the first and second networks are physically independent of one another;
• wherein communications conducted on the first network are conducted logically independent of communications conducted on the second network, and wherein communications conducted on the second network are conducted logically independent of communications conducted on the first network.