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US 12,561,201 B2Granted
Error protection for managed memory devices
AssigneeMicron Technology, Inc.
InventorsChandrakanth Rapalli, Yoav Weinberg, Tal Sharifie
Life of this patent
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AssigneeMicron Technology, Inc.
InventorsChandrakanth Rapalli, Yoav Weinberg, Tal Sharifie
Estimating the term…
Methods, systems, and devices for error protection for managed memory devices are described. In some examples, a memory system may receive data units from a host device. The data units may include respective sets of parity bits, and the memory system may perform an error detection operation on the data units. A first controller of the memory system may generate a protocol unit using data (e.g., a subset of data) from the data units. The protocol unit may include a set of parity bits (e.g., a different set of parity bits), and a second controller of the memory system may perform an error detection operation on the protocol unit. The second controller of the memory system may generate a data storage unit using data (e.g., a subset of data) from the protocol unit, and may store the data unit and another set of parity bits to a memory device.
A memory system, comprising:
A method at a memory system comprising one or more memory devices, comprising:
A non-transitory computer-readable medium storing code for memory operations at a memory system comprising one or more memory devices, the code comprising instructions executable by one or more processors to:
Dependencies are inferred from the claim text.