Apparatus and method for improving instruction fusion, fracture, and binary translation

An electronic, digital data processor comprising:

• a pipelined central processing unit comprising:
• an instruction fetch facility adapted to:
• fetch a stream of instructions;
• and
• output said fetched instructions in a predetermined order;
• an instruction decode facility, coupled to the instruction fetch facility, and adapted to:
• receive the fetched instructions output from the instruction fetch facility;
• decode simultaneously M of said received fetched instructions;
• receive dynamically an instruction transform comprising at least one decoded transform instruction;
• receive dynamically an instruction transform select signal having a selected one of first and second states;
• and
• either:
• output said decoded instructions in response to receiving said instruction transform select signal in said first state;
• or:
• output said instruction transform in response to receiving said instruction transform select signal in said second state;
• and
• an instruction execution facility comprising an instruction execution pipeline, coupled to the instruction decode facility, and adapted to:
• receive the decoded instructions output from the instruction decode facility;
• execute said decoded instructions in the instruction execution pipeline;
• detect a predetermined pipeline event in the instruction execution pipeline;
• and
• either:
• output a pipeline event signal in a third state if said predetermined dynamic condition in the instruction execution pipeline is not detected;
• or:
• output the pipeline event signal in a fourth state if said predetermined dynamic condition in the instruction execution pipeline is detected;
• and
• an instruction transform facility, coupled to the instruction decode facility and to the instruction execution facility, and adapted to:
• receive the decoded instructions output from the instruction decode facility;
• detect in the received decoded instructions a first predetermined sequence of N of said received decoded instructions, where N is greater than 1 and no greater than M;
• develop said instruction transform of said first predetermined sequence of N of said received decoded instructions;
• receive the pipeline event signal output from the instruction execution facility;
• and
• either:
• output said instruction transform signal in said first state in response to receiving said pipeline event signal in said third state;
• or:
• output said instruction transform signal in said second state in response to receiving said pipeline event signal in said fourth state.