Stacked transistors with metal vias

A semiconductor structure, comprising:

• a first stacked device structure comprising:
• a first field-effect transistor comprising a first source/drain region;
• a second field-effect transistor vertically stacked above the first field-effect transistor, the second field-effect transistor comprising a second source/drain region;
• a frontside source/drain contact disposed on a first portion of a sidewall and a top surface of the second source/drain region;
• and
• a first metal via connected to the frontside source/drain contact and to a first backside power line;
• and
• a second stacked device structure adjacent the first stacked device structure comprising:
• a third field-effect transistor comprising a third source/drain region;
• a fourth field-effect transistor vertically stacked above the third field-effect transistor, the fourth field-effect transistor comprising a fourth source/drain region;
• a first backside source/drain contact disposed on a second portion of a sidewall and a bottom surface of the third source/drain region;
• a second metal via connected to the first backside source/drain contact and to a back-end-of-the-line layer;
• a bottom dielectric insulator layer disposed on another portion of the bottom surface of the third source/drain region;
• a first sidewall spacer and a second sidewall spacer disposed on opposing sidewalls of the first stacked device structure and the second stacked device structure;
• and
• a dielectric fill disposed between the first sidewall spacer and the second sidewall spacer.

A semiconductor structure, comprising:

• a first stacked transistor comprising:
• a first nanosheet field-effect transistor disposed on a first bottom dielectric insulator layer, the first nanosheet field-effect transistor comprising a first gate structure;
• and
• a second nanosheet field-effect transistor device stacked above the first nanosheet field-effect transistor, the second nanosheet field-effect transistor device comprising a second gate structure having first sidewall spacers;
• a second stacked transistor adjacent the first stacked transistor comprising:
• a third nanosheet field-effect transistor disposed on a second bottom dielectric insulator layer, the third nanosheet field-effect transistor comprising a third gate structure;
• and
• a fourth nanosheet field-effect transistor device stacked above the third nanosheet field-effect transistor, the fourth nanosheet field-effect transistor device comprising a fourth gate structure having second sidewall spacers;
• a third sidewall spacer and a fourth sidewall spacer disposed on opposing sidewalls of the first stacked transistor and the second stacked transistor;
• and
• a first metal via disposed between the third sidewall spacer and the fourth sidewall spacer.