US 12,557,617 B2Granted

Continuous gate and fin spacer for advanced integrated circuit structure fabrication

AssigneeIntel Corporation

InventorsHeidi M. Meyer, Ahmet Tura, Byron Ho, Subhash Joshi, Michael L. Hattendorf, Christopher P. Auth

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Abstract

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An insulating structure is directly adjacent sidewalls of the lower fin portion of the fin. A first gate electrode is over the upper fin portion and over a first portion of the insulating structure. A second gate electrode is over the upper fin portion and over a second portion of the insulating structure. A first dielectric spacer is along a sidewall of the first gate electrode. A second dielectric spacer is along a sidewall of the second gate electrode, the second dielectric spacer continuous with the first dielectric spacer over a third portion of the insulating structure between the first gate electrode and the second gate electrode.

Claims20

Dependent claims

An integrated circuit structure, comprising:

a three-dimensional body, the three-dimensional body having a lower portion and an upper portion, the upper portion having a first region, a second region, and a third region, the second region between and continuous with the first region and the third region, wherein the first region, the second region, and the third region of the upper portion have a same semiconductor composition, the first region having a first channel region, and the third region having a second channel region;
an insulating structure directly adjacent sidewalls of the lower portion of the three-dimensional body;
a first gate electrode completely surrounding the first channel region of the first region of the upper portion of the three-dimensional body and over a first portion of the insulating structure;
a second gate electrode over the completely surrounding the second channel region of the third region of the upper portion of the three-dimensional body and over a second portion of the insulating structure;
a first dielectric spacer along a sidewall of the first gate electrode;
a second dielectric spacer along a sidewall of the second gate electrode;
and
a third dielectric spacer along a sidewall of the second region of the upper portion of the three-dimensional body and not on a top surface of the three-dimensional body, the third dielectric spacer continuous with the first and second dielectric spacers, wherein the first dielectric spacer, the second dielectric spacer, and the third dielectric spacer are a single continuous material, the single continuous material over a third portion of the insulating structure between the first gate electrode and the second gate electrode, wherein the single continuous material covers an entirety of the third portion of the insulating structure between the first gate electrode and the second gate electrode, and wherein a portion of the single continuous material is conformal with a non-planar uppermost surface of the third portion of the insulating structure.

5 more elements

An integrated circuit structure, comprising:

a first three-dimensional body, the first three-dimensional body having a lower portion and an upper portion, the upper portion of the first three-dimensional body having a first region and a second region continuous with the first region, wherein the first region and the second region of the upper portion of the first three-dimensional body have a same semiconductor composition, and wherein the first region of the upper portion of the first three-dimensional body has a first channel region;
a second three-dimensional body, the second three-dimensional body having a lower portion and an upper portion, the upper portion of the second three-dimensional body having a first region and a second region continuous with the first region, wherein the first region and the second region of the upper portion of the second three-dimensional body have a same semiconductor composition, and wherein the first region of the upper portion of the second three-dimensional body has a second channel region;
an insulating structure directly adjacent sidewalls of the lower portion of the first three-dimensional body and directly adjacent sidewalls of the lower portion of the second three-dimensional body;
a gate electrode completely surrounding the first channel region of the first region of the upper portion of the first three-dimensional body, completely surrounding the second channel region of the first region of the upper portion of the second three-dimensional body, and over a first portion of the insulating structure;
a first dielectric spacer along a sidewall of the second region of the upper portion of the first three-dimensional body and not on a top surface of the first three-dimensional body;
a second dielectric spacer along a sidewall of the second region of the upper portion of the second three-dimensional body and not on a top surface of the second three-dimensional body;
and
a third dielectric spacer along a sidewall of the gate electrode, wherein the third dielectric spacer, the second dielectric spacer and the first dielectric spacer are a single continuous material, the single continuous material over a second portion of the insulating structure between the first three-dimensional body and the second three-dimensional body, wherein the single continuous material covers an entirety of the second portion of the insulating structure between the first three-dimensional body and the second three-dimensional body, and wherein the single continuous material is conformal with a non-planar uppermost surface of the second portion of the insulating structure.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/376,763Filed 4 Oct 2023 · continuation
Priority: 30 Nov 2017
Published: US 2024/0038578 A11 Feb 2024
Granted: 17 Feb 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification40 codes

H10W 10/014
Of isolation regions comprising dielectric materials: using trench refilling with dielectric materials, e.g. shallow trench isolations
H10B 10/12
Static random access memory [SRAM] devices: comprising a MOSFET load element
H10D 1/474
Resistors having no potential barriers: comprising refractory metals, transition metals, noble metals, metal compounds or metal alloys, e.g. silicides
H10D 30/024
Of FETs having insulated gates [IGFET]: of fin field-effect transistors [FinFET]

Family

Application62/593,149Us provisional application · filed 30 Nov 2017
Application15/859,323Parent of this division · filed 29 Dec 2017
Application17/890,969Parent of this continuation · filed 18 Aug 2022
US 11,462,436 B2Parent of this division · filed 4 Oct 2022
US 2024/0038578 A1Pre-grant publication · published 1 Feb 2024
US 11,837,456 B2Parent of this continuation
Application17/890,969Parent of this division
US 2019/0164809 A1Published application
US 2022/0406650 A1Published application
US 12,557,617 B2This patent

From the US filing history. Foreign family members aren’t listed.