Silicon-on-insulator substrate including trap-rich layer and methods for making thereof

A silicon-on-insulator substrate, comprising:

• a layered structure including, in layered order:
• (1) a high-resistivity base layer having a first side and a second side opposite the first side,
• wherein the high-resistivity base layer comprises silicon, and
• wherein the high-resistivity base layer has
• (a) a resistivity in a range of from 50 to 100 ohm-meters, and
• (b) a thickness in a range of from 500 to 700 microns;
• (2) a trap-rich layer having a first side and a second side opposite the first side of the trap-rich layer,
• wherein the trap-rich layer is positioned on the first side of the high-resistivity base layer such that the second side of the trap-rich layer contacts the first side of the high-resistivity base layer,
• wherein the trap-rich layer comprises silicon nitride, and
• wherein the trap-rich layer has
• (i) a thickness that is in a range of 100 Angstroms to 1000 Angstroms, and
• (ii) a trap density that is in a range of 0.8*1010 cm2 eV−1 to 1.2*1010 cm2 eV−1;
• (3) a silicon dioxide layer positioned on the first side of the trap-rich layer,
• wherein the silicon dioxide layer has a thickness that is in a range of from 1000 to 5000 angstroms;
• and
• (4) a transfer layer positioned on the silicon dioxide layer,
• wherein the transfer layer comprises a silicon wafer, and
• wherein the transfer layer has a thickness that is a range of from 500 to 5000 angstroms.