Semiconductor on insulator structure comprising a buried high resistivity layer

A method of preparing a first multilayer structure and a second multilayer structure in parallel, the method comprising:

• cleaving a semiconductor on insulator structure comprising:
• (a) a single crystal semiconductor handle substrate comprising two major, generally parallel surfaces, one of which is a front surface of the single crystal semiconductor handle substrate and the other of which is a back surface of the single crystal semiconductor handle substrate, a circumferential edge joining the front and back surfaces of the single crystal semiconductor handle substrate, a central plane between the front surface and the back surface of the single crystal semiconductor handle substrate, and a bulk region between the front and back surfaces of the single crystal semiconductor handle substrate;
• (b) a handle dielectric layer in interfacial contact with the front surface of the single crystal semiconductor handle substrate;
• and (c) a high resistivity single crystal semiconductor handle layer in interfacial contact with the handle dielectric layer, wherein the high resistivity single crystal semiconductor handle layer has a minimum bulk resistivity of at least about 500 ohm-cm and has a handle cleave plane and further wherein cleaving at the handle cleave plane separates the semiconductor on insulator structure into a first cleaved structure and a second cleaved structure, wherein:
• the first cleaved structure comprises the single crystal semiconductor handle substrate, the handle dielectric layer in interfacial contact with the front surface of the single crystal semiconductor handle substrate, and a first portion of the high resistivity single crystal semiconductor handle layer in interfacial contact with the handle dielectric layer, wherein the first portion of the high resistivity single crystal semiconductor handle layer has a roughened front surface having a surface roughness of at least about 0.1 micrometers as measured according to the root mean square method over a surface area of at least 30 micrometers by 30 micrometers;
• and
• the second cleaved structure comprises a second portion of the high resistivity single crystal semiconductor handle layer, wherein the second portion of the high resistivity single crystal semiconductor handle layer has a roughened front surface having a surface roughness of at least about 0.1 micrometers as measured according to the root mean square method over a surface area of at least 30 micrometers by 30 micrometers;
• forming a first charge trapping layer over the roughened front surface of the first portion of the high resistivity single crystal semiconductor handle layer of the first cleaved structure and a second charge trapping layer over the roughened front surface of the second portion of the high resistivity single crystal semiconductor handle layer of the second cleaved structure, wherein each of the first and second charge trapping layers comprises polycrystalline silicon, the polycrystalline silicon comprising grains having a plurality of random crystal orientations and having a grain size between about 10 nanometers and about 3 micrometers;
• bonding a front surface of a first single crystal semiconductor donor substrate to the first charge trapping layer to thereby form a first bonded structure, and a front surface of a second single crystal semiconductor donor substrate to the second charge trapping layer to thereby form a second bonded structure, wherein each of the first and second single crystal semiconductor donor substrates comprises two major, generally parallel surfaces, one of which is the front surface of the respective semiconductor donor substrate and the other of which is a back surface of the respective semiconductor donor substrate, a circumferential edge joining the front and back surfaces of the respective semiconductor donor substrate, and a central plane between the front and back surfaces of the respective semiconductor donor substrate, wherein the first bonded structure comprises the first cleaved structure, the first charge trapping layer, and the first single crystal semiconductor donor substrate, and the second bonded structure comprises the second cleaved structure, the second charge trapping layer, and the second single crystal semiconductor donor substrate.