Multilayer isolation structure for high voltage silicon-on-insulator device

A method comprising:

• receiving a semiconductor-on-insulator substrate that includes a first semiconductor layer, a second semiconductor layer disposed over the first semiconductor layer, and an insulator layer disposed between the first semiconductor layer and the second semiconductor layer;
• and
• forming an isolation structure that surrounds an active region of the semiconductor-on-insulator substrate, wherein the isolation structure extends through the second semiconductor layer and the insulator layer of the semiconductor-on-insulator substrate to the first semiconductor layer of the semiconductor-on-insulator substrate, and further wherein the isolation structure includes:
• a first insulator sidewall spacer,
• a second insulator sidewall spacer, and
• a multilayer silicon-comprising isolation structure disposed between the first insulator sidewall spacer and the second insulator sidewall spacer, wherein the multilayer silicon-comprising isolation structure includes a top polysilicon portion disposed over a bottom monocrystalline silicon portion.

A method comprising:

• receiving a semiconductor structure, wherein the semiconductor structure includes a first semiconductor layer, a dielectric layer over the first semiconductor layer, and a second semiconductor layer over the dielectric layer;
• and
• processing the semiconductor structure to form an isolation ring over the first semiconductor layer, wherein the dielectric layer and the second semiconductor layer each extend from a first inner sidewall of the isolation ring to a second inner sidewall of the isolation ring and further wherein the isolation ring has:
• a dielectric ring, and
• a semiconductor ring disposed in the dielectric ring, wherein the semiconductor ring includes a top polysilicon portion over a bottom silicon portion, wherein the semiconductor ring is formed by:
• forming a trench that extends through the second semiconductor layer and the dielectric layer, wherein the trench exposes the first semiconductor layer;
• depositing monocrystalline silicon in a bottom of the trench without depositing the monocrystalline silicon in a top of the trench, wherein the monocrystalline silicon forms the bottom silicon portion of the semiconductor ring;
• depositing polysilicon in the top of the trench over the monocrystalline silicon and over a top of the second semiconductor layer, wherein the polysilicon forms the top polysilicon portion of the semiconductor ring;
• and
• removing the polysilicon from over the top of the second semiconductor layer.