Contaminant collection on SOI
AssigneeTexas Instruments Incorporated
InventorsHonglin Guo, Frank John Sweeney
Life of this patent
Estimating the term…
Abstract
An integrated circuit includes an SOI substrate having a semiconductor layer over a buried insulator layer. An electronic device has an NWELL region in the semiconductor layer, a dielectric over the NWELL region, and a polysilicon plate over the dielectric. A white space region adjacent the electronic device includes a first P-type region in the semiconductor layer and adjacent the surface. The P-type region has a first sheet resistance and the NWELL region has a second sheet resistance that is greater than the first sheet resistance.
Claims12
An integrated circuit, comprising:
- a semiconductor-on-insulator (SOI) substrate having a semiconductor layer over a buried insulator layer;
- an electronic device having an N-type well (NWELL) region in the semiconductor layer, a dielectric on a surface of the semiconductor layer and over the NWELL region, and a polysilicon plate over the dielectric;
- and
- a white space region adjacent a side of the electronic device, the white space region including a first P-type region in the semiconductor layer, the first P-type region having a first sheet resistance and the NWELL region having a second sheet resistance that is greater than the first sheet resistance.
An integrated circuit, comprising:
- an epitaxial layer over a buried oxide layer;
- an N-type well (NWELL) region in the epitaxial layer;
- an oxide layer on the NWELL region;
- a polysilicon plate on the oxide layer;
- and
- a DWELL region adjacent the NWELL region in the epitaxial layer, the DWELL region including boron having a first dopant dose and the NWELL region having a second dopant dose that is less than the first dopant dose, wherein the DWELL region is in a white space region.
Dependencies are inferred from the claim text.