Semiconductor device and manufacturing method thereof

A semiconductor device, comprising:

• a channel strip of a two-dimensional semiconductor material;
• metallic layers of a two-dimensional metallic material disposed in stacks at opposite sides of the channel strip;
• metal blocks disposed on the metallic layers;
• a gate dielectric layer disposed on the channel strip and between the metallic layers;
• a gate electrode disposed on the gate dielectric layer;
• and
• strips of the two-dimensional semiconductor material respectively disposed below the metal blocks,
• wherein the metallic layers are interposed between the strips of the two-dimensional semiconductor material and the channel strip, the channel strip is physically contactless with the strips of the two-dimensional semiconductor material, the metallic layers are of different materials from the strips of the two-dimensional semiconductor material, and a first portion of the gate dielectric layer that is sandwiched between the metallic layers has a first width smaller than a second width of a second portion of the gate dielectric layer that is sandwiched between the metal blocks.

A semiconductor device, comprising:

• a channel strip of a two-dimensional semiconductor material;
• metallic layers of a two-dimensional metallic material disposed in stacks at opposite sides of the channel strip;
• metal blocks disposed on the metallic layers;
• a gate dielectric layer disposed on the channel strip and between the metallic layers;
• a gate electrode disposed on the gate dielectric layer;
• and
• strips of the two-dimensional semiconductor material respectively disposed below the metal blocks,
• wherein the metallic layers are located between the strips of the two-dimensional semiconductor material and the channel strip to separate the channel strip and the strips of the two-dimensional semiconductor material, the metallic layers are of different materials from the strips of the two-dimensional semiconductor material, and the channel strip is physically isolated from and contactless with the strips of the two-dimensional semiconductor material,
• wherein a first portion of the gate dielectric layer that is sandwiched between the metallic layers has a first width smaller than a second width of a second portion of the gate dielectric layer that is sandwiched between the metal blocks.