Enhancement mode transistor with a robust gate and method

A structure comprising:

• a barrier layer with alternating first barrier portions and second barrier portions, wherein the first barrier portions are within active device regions of enhancement mode transistors and the second barrier portions are external to side boundaries of the active device regions of the enhancement mode transistors, and wherein each first barrier portion is positioned laterally between and thicker than adjacent second barrier portions;
• a source terminal and a drain terminal extending at least partially through the barrier layer, wherein the source terminal and the drain terminal are immediately adjacent to the first portions and traverse at least the active device regions of the enhancement mode transistors and an active device region of a depletion mode transistor between the enhancement mode transistors;
• gates within the active device regions of the enhancement mode transistors, respectively, wherein the gates are positioned laterally between the source terminal and the drain terminal, and wherein each gate within a corresponding active device region has stepped opposing end walls adjacent side boundaries of the corresponding active device region and includes:
• a semiconductor layer on a first barrier portion, wherein the semiconductor layer has, above the first barrier portion, a first semiconductor portion and second semiconductor portions and wherein the first semiconductor portion is positioned laterally between and thicker than the second semiconductor portions;
• and
• a gate conductor layer on the first semiconductor portion, wherein the first semiconductor portion is wider than the gate conductor layer and the gate conductor layer only partially traverses the corresponding active device region in a direction parallel to the source terminal and the drain terminal and is spaced apart from the side boundaries of the corresponding active device region;
• and
• a conformal dielectric layer over the gates and further on the second barrier portions on opposing sides of the gates.

A method comprising:

• forming a barrier layer having a first barrier portion within an active device region and second barrier portions external to side boundaries of the active device region, wherein the first barrier portion is positioned laterally between and thicker than the second barrier portions;
• forming a source terminal and a drain terminal extending at least partially through the barrier layer, wherein the source terminal and the second terminal are immediately adjacent to the first barrier portion and traverse the active device region;
• and
• forming a gate within the active device region and positioned laterally between the source terminal and the drain terminal, wherein the gate has stepped opposing end walls adjacent side boundaries of the active device region, and wherein the gate includes:
• a semiconductor layer on the first barrier portion, wherein the semiconductor layer has, above the first barrier portion, a first semiconductor portion and second semiconductor portions, and wherein the first semiconductor portion is positioned laterally between and thicker than the second semiconductor portions;
• and
• a gate conductor layer on the first semiconductor portion, wherein the first semiconductor portion is wider than the gate conductor layer and the gate conductor layer only partially traverses the active device region in a direction parallel to the source terminal and the drain terminal and is spaced apart from the side boundaries of the active device region.