US 12,557,297 B2 · Leveling dielectric surfaces for contact formation with embedded memory arrays

Abstract

An approach providing a semiconductor structure that provides a self-leveling, flowable, dielectric material for a gap fill material between vertical structures in many emerging non-volatile memory devices that are being formed with vertical structures for increasing memory device density. The semiconductor structure provides a flat dielectric surface between a plurality of contacts in a back end of the line metal layer in both the memory region and in the logic region of the semiconductor structure. The semiconductor structure includes a first portion of the plurality of contacts that each connect to a pillar-based memory device in an array of pillar-based memory devices. The first portion of the contacts that each connect to a pillar-based memory device in the array of memory devices reside in a conventional interlayer dielectric material under the self-leveling dielectric material. The flowable, self-leveling material provides a flat dielectric surface during contact formation.

Claims19

Dependent claims

A semiconductor structure, the semiconductor structure comprising:

a flat dielectric surface of a first dielectric material between a plurality of contacts in a back end of line metal layer of a semiconductor structure, wherein a first portion of the plurality of contacts each connect to a pillar-based memory device in an array of pillar-based memory devices, a second portion of the plurality of contacts each connect to a contact in a logic region of the semiconductor structure, and the flat dielectric surface is at a same level in the logic region and around the pillar-based memory devices;
and
a second dielectric material in a continuous layer under the first dielectric material, the first portion of the plurality of contacts, and the second portion of the plurality of contacts, and surrounds sidewalls of the first portion of the plurality of contacts in a memory region of the semiconductor structure, and wherein the first dielectric material surrounds sidewalls of the second portion of the plurality of contacts.

A semiconductor structure, the semiconductor structure comprising:

a back end of line metal layer, comprising:
contacts in a memory region connecting to a plurality of pillar-based memory devices;
a first interlayer dielectric (ILD) material surrounding the contacts, wherein the first ILD material leaves gaps between the contacts;
and
a self-leveling dielectric material filling the gaps in the first ILD material;
and
an encapsulation dielectric material surrounding each of the plurality of pillar-based memory devices, wherein the self-leveling dielectric material is over the encapsulation dielectric material, and a plurality of top surfaces of:
i) the self-leveling dielectric material, ii) the contacts, and iii) the first ILD material each have a same height.

5 more elements

Dependencies are inferred from the claim text.

Leveling dielectric surfaces for contact formation with embedded memory arrays

Life of this patent

Leveling dielectric surfaces for contact formation with embedded memory arrays

Life of this patent

Abstract

Claims19