Printed circuit board having cutting position identification mark and alignment mark and semiconductor package having the same
AssigneeSamsung Electronics Co., Ltd.
InventorsKanggyune Lee, Hyunggil Baek, Youngja Kim, Seungjin Lee
Life of this patent
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Abstract
A printed circuit board includes a substrate base; a plurality of ball lands arranged on a surface of the substrate base; a cutting position identification mark disposed on a corner of the surface of the substrate base; and at least one alignment mark disposed on the surface of the substrate base to be spaced apart from the ball lands and exposed to the outside, wherein top surfaces of the ball lands and a top surface of the at least one alignment mark are at substantially the same vertical level and the ball lands and the at least one alignment mark include the same material.
Claims18
A printed circuit board comprising:
- a substrate base;
- a plurality of ball lands arranged on a surface of the substrate base;
- a cutting position identification mark identifying a cut corner of the substrate base, the cutting position identification mark disposed on the surface of the substrate base at the cut corner;
- and
- an alignment mark disposed on the surface of the substrate base, spaced apart from the ball lands, and exposed by the surface of the substrate base,
- wherein top surfaces of the ball lands and a top surface of the alignment mark are at substantially the same vertical level and the ball lands and the alignment mark comprise the same material.
A printed circuit board for a semiconductor package, the printed circuit board comprising:
- a substrate base in which a plurality of wiring layers are vertically stacked;
- a plurality of ball lands arranged at a bottommost layer of the wiring layers;
- and
- an alignment mark disposed at the bottommost layer of the wiring layers and spaced apart from the ball lands,
- wherein the alignment mark is exposed by the substrate base,
- wherein the alignment mark identifies a center point of the printed circuit board relative to the plurality of ball lands,
- wherein a top surface of the alignment mark comprises the same material as the wiring layers, and
- wherein the top surface of the alignment mark comprises a resin, a solder resist, or an organic solderability preservative (OSP).
A semiconductor package comprising:
- a printed circuit board having a top surface and a bottom surface;
- a semiconductor chip mounted on the top surface of the printed circuit board;
- a plurality of ball lands located on the bottom surface of the printed circuit board;
- a plurality of solder balls attached to the ball lands;
- a cutting position identification mark disposed at one corner of the bottom surface of the printed circuit board;
- and
- an alignment mark disposed on the bottom surface of the printed circuit board, spaced apart from the ball lands, and exposed by the printed circuit board, and
- bottom surfaces of the ball lands and a bottom surface of the alignment mark are at substantially the same vertical level and the ball lands and the alignment mark comprise the same material.
Dependencies are inferred from the claim text.