Successive approximation register analog-to-digital converter and comparison method

A successive approximation register analog-to-digital converter, comprising:

• a comparator;
• a capacitor array, comprising a first capacitor array and a second capacitor array, wherein the first capacitor array and the second capacitor array each comprise n−1 weighted capacitors and a charge transfer capacitor, a first plate of the first capacitor array is connected to an in-phase input terminal of the comparator, a first plate of the second capacitor array is connected to an inverting input terminal of the comparator, n is an integer greater than or equal to 3, the n−1 weighted capacitors are successively arranged in descending order of capacitance, a first weighted capacitor has largest capacitance, and a last weighted capacitor has smallest capacitance;
• a switch, comprising a first channel switch, a second channel switch, a third channel switch, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a first switch array, and a second switch array, wherein a first common-mode voltage is connected to the in-phase input terminal of the comparator after passing through the first channel switch connected in series, the first common-mode voltage is connected to the inverting input terminal of the comparator after passing through the second channel switch connected in series, the third channel switch is connected in series between the in-phase input terminal of the comparator and the inverting input terminal of the comparator, a second plate of the first weighted capacitor in the first capacitor array is further connected to a first output terminal of an differential input signal via the first switch connected in series, a second plate of the first weighted capacitor in the second capacitor array is further connected to a second output terminal of the differential input signal via the second switch connected in series, a second plate of the charge transfer capacitor in the first capacitor array is further connected to the first output terminal of the differential input signal via the third switch connected in series, a second plate of the charge transfer capacitor in the second capacitor array is further connected to the second output terminal of the differential input signal via the fourth switch connected in series, the second plate of the first weighted capacitor in the capacitor array is connected to a second common-mode voltage by using the fifth switch, the second plate of the charge transfer capacitor in the capacitor array is connected to the second common-mode voltage by using the sixth switch, a second plate of the last weighted capacitor in the capacitor array is grounded, a second plate of an mth weighted capacitor in the capacitor array is connected to the second common-mode voltage by using a corresponding switch in the first switch array, the second plate of the mth weighted capacitor in the capacitor array is further connected to a reference voltage by using a corresponding switch in the second switch array, and m=2, 3, . . . , n−2;
• and
• a logic control module, wherein an input terminal of the logic control module is connected to an output terminal of the comparator, an output terminal of the logic control module is connected to the second switch array, each switch in the second switch array is controlled based on an output signal of the comparator, so as to perform successive approximation conversion, and successive approximation comparison is performed based on the comparator, so as to implement analog-to-digital conversion.