Analog-to-digital converter (ADC) clock phase continuity across user equipment microsleep mode

An apparatus, comprising:

• a first synchronizer configured to synchronize a frequency divider reset signal with a reference clock signal or a frequency divided reference clock signal to generate a reference clock domain frequency divider reset signal;
• a set of delay buffers configured to generate a set of delayed staggered reference clock domain frequency divider reset signals based on the reference clock domain frequency divider reset signal;
• a set of second synchronizers configured to synchronize the set of delayed staggered reference clock domain frequency divider reset signals with a phase lock loop (PLL) clock signal to output a set of PLL clock domain frequency divider reset signals;
• a phase detector configured to generate a phase difference signal related to a phase difference between respective clocking edges of the reference clock signal or the frequency divided reference clock signal and the PLL clock signal;
• a phase corrector configured to generate a select signal based on the phase difference signal;
• and
• a multiplexer configured to output one of the set of PLL clock domain frequency divider reset signals based on the select signal.