Active phase monitor for clock switchover

A device comprising:

• a timing circuit including at least a digital phase-locked loop (DPLL);
• and
• a plurality of transceivers configured to:
• recover a plurality of reference clock signals;
• and
• transmit the plurality of reference clock signals to the timing circuit,
• wherein the DPLL is configured to:
• receive the plurality of reference clock signals;
• determine at least one phase offset among a plurality of reference clock signals;
• generate an output clock signal using a primary reference clock for a phase-locked loop (PLL) in the DPLL, wherein the primary reference clock is among the plurality of reference clock signals;
• determine a failure of the primary reference clock;
• and
• in response to the failure of the primary reference clock, generate the output clock signal using a specific phase offset and a secondary reference clock for the PLL, wherein the specific phase offset is among the at least one phase offset determined by the DPLL prior to the failure of the primary reference clock, the specific phase offset is between the primary reference clock and the secondary reference clock, and the secondary reference clock is among the plurality of reference clock signals.

A method comprising:

• receiving a plurality of reference clock signals;
• determining at least one phase offset among the plurality of reference clock signals;
• generating an output clock signal using a primary reference clock among the plurality of reference clock signals;
• determining a failure of a primary reference clock for a phase-locked loop (PLL);
• and
• in response to the failure of the primary reference clock, generating the output clock signal using a specific phase offset and a secondary reference clock for the PLL, wherein the specific phase offset is among the at least one phase offset determined prior to the failure of the primary reference clock, the specific phase offset is between the primary reference clock and the secondary reference clock, and the secondary reference clock is among the plurality of reference clock signals.