Clock multiplexing circuit, clock distribution circuit, and semiconductor apparatus including the clock multiplexing circuit
AssigneeSK hynix Inc.
InventorJi Hyo Kang
Life of this patent
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Abstract
A clock multiplexing circuit includes: a mode control unit configured to generate first enable signals and second enable signals in response to mode control signals; a first multiplexing unit configured to convert first input signals having a current mode logic (CML) level into complementary metal-oxide semiconductor (CMOS) level-signals in response to activation of the first enable signals, and to output the CMOS level-signals; and a second multiplexing unit configured to buffer and output second input signals having the CMOS level in response to the first enable signals and the second enable signals.
Claims16
A clock multiplexing circuit comprising:
- a mode control unit configured to generate first enable signals and second enable signals in response to mode control signals;
- a first multiplexing unit configured to convert first input signals having a current mode logic (CML) level into complementary metal-oxide semiconductor (CMOS) level-signals in response to activation of the first enable signals, and to output the CMOS level-signals;
- and
- a second multiplexing unit configured to buffer and output second input signals having the CMOS level in response to the first enable signals and the second enable signals.
A clock distribution circuit comprising:
- a first clock processing circuit configured to divide and output first external clock signals when mode control signals have a value defining a first mode;
- a second clock processing circuit configured to multiply and output the first external clock signals and second external clock signals when the mode control signals have a value defining a second mode;
- and
- a clock multiplexing circuit configured to convert the output of the first clock processing circuit into complementary metal-oxide semiconductor (CMOS) level-signals and output the CMOS level-signals when the mode control signals have the value defining the first mode, and to buffer and output the output of the second clock processing circuit when the mode control signals have the value defining the second mode.
A semiconductor apparatus comprising:
- a plurality of input and output (input/output) terminals configured to transmit and receive data according to multiphase clock signals;
- a global clock distribution circuit configured to convert first preliminary multiphase clock signals, which are generated by dividing first external clock signals, into and output the complementary metal-oxide semiconductor (CMOS) level-signals when mode control signals have a value defining a first mode, and to buffer and output second preliminary multiphase clock signals generated by multiplying the first external clock signals and second external clock signals when the mode control signals have a value defining a second mode;
- and
- a local clock distribution circuit configured to distribute, as the multiphase clock signals, the first preliminary multiphase clock signals and the second preliminary multiphase clock signals to the plurality of input/output terminals.
Dependencies are inferred from the claim text.