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US 12,556,180 B2Granted
Hot carrier injection hardened physically unclonable function circuit
AssigneeIntel Corporation
InventorsRachael Parker, Jyothi Bhaskarr Velamala
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Abstract
Various embodiments provide apparatuses, systems, and methods for a hot carrier injection (HCI) physically unclonable function (PUF) circuit. For example, described herein is a HCI PUF circuit with n-type metal oxide semiconductor (NMOS) transistors and a Pi-shaped reset structure. Other embodiments may be described and claimed.
Claims22
A physically unclonable function (PUF) circuit comprising a PUF cell that includes:
- an n-type metal-oxide-semiconductor (NMOS) latch circuit to evaluate to a first logic value at a first node and a second logic value at a second node, wherein the second logic value is the inverse of the first logic value;
- a reset transistor coupled between the first node and the second node;
- a first reset-to-ground transistor coupled between the first node and ground;
- and
- a second reset-to-ground transistor coupled between the second node and ground.
2 more elements
An apparatus comprising:
- a physically unclonable function (PUF) cell that includes:
- a first n-type metal-oxide semiconductor (NMOS) transistor coupled between a first node and ground;
- a second NMOS transistor coupled between a second node and ground, wherein a gate terminal of the first NMOS transistor is coupled to the second node and a gate terminal of the second NMOS transistor is coupled to the first node;
- a third NMOS transistor coupled between a supply rail and the first node;
- a fourth NMOS transistor coupled between the supply rail and the second node, wherein gate terminals of the third and fourth NMOS transistors are coupled to the supply rail,
- a reset transistor coupled between the first node and the second node;
- and
- a first reset-to-ground (r2gnd) transistor coupled between the first node and ground;
- and
- a second r2gnd transistor coupled between the second node and ground;
- and
- control circuitry coupled to the PUF cell, the control circuitry to:
- provide a supply voltage to the supply rail with a first voltage level, the supply voltage to energize the PUF cell to enter an evaluated state with a first logic value at the first node and a second logic value at the second node, wherein the second logic value is the inverse of the first logic value;
- and
- subsequently raise the supply voltage to a second voltage level that is higher than the first voltage level while the PUF cell remains in the evaluated state.
12 more elements
A computer system comprising:
- an integrated circuit that includes:
- one or more processors;
- a physically unclonable function (PUF) circuit that includes an array of PUF cells, wherein individual PUF cells of the array of PUF cells include:
- a latch circuit to evaluate to a first logic value at a first node and a second logic value at a second node, wherein the second logic value is the inverse of the first logic value;
- a reset transistor coupled between the first node and the second node;
- a first reset-to-ground (r2gnd) transistor coupled between the first node and ground;
- and
- a second reset-to-ground (r2gnd) transistor coupled between the second node and ground, wherein gate terminals of the first and second r2gnd transistors are to receive a r2gnd control signal;
- a memory coupled to the one or more processors;
- and
- a communication interface coupled to the one or more processors.
8 more elements
Dependencies are inferred from the claim text.