Power amplification device, power amplification system, and operation method thereof

An operation method of a power amplification device, comprising:

• receiving a transmit power level;
• determining a plurality of circuit configurations for a plurality of power amplification circuits in the power amplification device based on the transmit power level, respectively, wherein when the transmit power level is changed, the plurality of circuit configurations for the plurality of power amplification circuits are also changed such that an output power of the power amplification device matches the transmit power level;
• and
• configuring the plurality of power amplification circuits using the plurality of circuit configurations, respectively,
• wherein the power amplification device comprises:
• the plurality of power amplification circuits configured to provide a plurality of amplified outputs based on a plurality of inputs, respectively;
• a power supply network coupled to the plurality of power amplification circuits, and configured to supply at least one of a plurality of power sources to the plurality of power amplification circuits;
• and
• a transformer network coupled to the plurality of power amplification circuits, and configured to provide the output power that matches the transmit power level based on the plurality of amplified outputs,
• wherein each power amplification circuit comprises a plurality of power amplifiers (PAS), and each PA comprises a plurality of sub-PAs having respective outputs coupled to an output port of the PA in parallel,
• wherein the plurality of sub-PAs comprises a first sub-PA and at least a second sub-PA,
• wherein the first sub-PA comprises a first NMOS transistor and a first PMOS transistor, and
• wherein the second sub-PA comprises a second NMOS transistor, a second PMOS transistor, and a switch coupled between the second NMOS transistor and the second PMOS transistor.

A power amplification system, comprising:

• a power amplification device, comprising:
• a plurality of power amplification circuits configured to provide a plurality of amplified outputs based on a plurality of inputs, respectively;
• a power supply network coupled to the plurality of power amplification circuits, and configured to supply at least one power source from a plurality of power sources to the plurality of power amplification circuits;
• and
• a transformer network coupled to the plurality of power amplification circuits, and configured to provide an output power that matches a transmit power level based on the plurality of amplified outputs,
• wherein each power amplification circuit comprises a plurality of power amplifiers (PAS), and each PA comprises a plurality of sub-PAs having respective outputs coupled to an output port of the PA in parallel,
• wherein the plurality of sub-PAs comprises a first sub-PA and at least a second sub-PA,
• wherein the first sub-PA comprises a first NMOS transistor and a first PMOS transistor, and
• wherein the second sub-PA comprises a second NMOS transistor, a second PMOS transistor, and a switch coupled between the second NMOS transistor and the second PMOS transistor;
• and
• a control unit coupled to the power amplification device, and comprising a memory storing code and a processor coupled to the memory, wherein when the code is executed, the processor is configured to:
• determine a plurality of circuit configurations for the plurality of power amplification circuits based on the transmit power level, respectively, wherein when the transmit power level is changed, the plurality of circuit configurations for the plurality of power amplification circuits are also changed such that the output power provided by the transformer network matches the transmit power level;
• and
• configure the plurality of power amplification circuits using the plurality of circuit configurations, respectively.