Logical memory repair with a shared physical memory

A method comprising:

• performing, by a memory built-in self-test controller, at least one test on multiple logical memories;
• identifying, by the memory built-in self-test controller, two or more faulty memory portions of at least one physical memory based on the performing;
• loading, by the memory built-in self-test controller, a first address register with a first faulty memory address and a second address register with a second faulty memory address based on the identifying;
• and
• arbitrating, by the at least one physical memory, access to at least one spare memory portion, which corresponds to the two or more faulty memory portions, responsive to the first faulty memory address conflicting with the second faulty memory address.

An apparatus comprising:

• a memory built-in self-test controller including circuitry configured to perform at least one test on multiple logical memories;
• and
• a memory cluster including:
• a shared bus interface coupled to the memory built-in self-test controller and configured to provide access to the multiple logical memories;
• and
• at least one physical memory coupled to the shared bus interface and configured to have two or more logical memories of the multiple logical memories overlaid thereon, the at least one physical memory including:
• one or more built-in self-repair registers configured to store one or more built-in self-repair parameters established by the memory built-in self-test controller based on the at least one test performed on the multiple logical memories;
• repair logic;
• an address decoder coupled to the repair logic;
• and
• arbitration logic coupled between the one or more built-in self-repair registers and the repair logic, the arbitration logic including circuitry configured to convert the built-in self-repair parameters into physical-memory level built-in self-repair parameters.