Memory device including page buffer circuit

A memory device comprising:

• a memory cell array comprising a plurality of memory cells;
• and
• a page buffer circuit comprising N page buffer units connected to the plurality of memory cells via N respective bit lines, wherein N is a natural number less than or equal to 8, and N cache latches respectively corresponding to the N page buffer units,
• wherein the memory device is configured such that, in a data sensing period, a sensing node of a first page buffer unit sensing data stored in at least one memory cell among the plurality of memory cells among the N page buffer units is actively electrically connected to a sensing node of at least a second page buffer unit other than the first page buffer unit among the N page buffer units.

A memory device comprising:

• a memory cell region comprising a plurality of memory cells and a first metal pad;
• and
• a peripheral circuit region comprising a second metal pad and being vertically connected to the memory cell region through the first metal pad and the second metal pad,
• wherein the peripheral circuit region comprises a page buffer circuit comprising a plurality of page buffer units arranged in a first horizontal direction and respectively connected to the plurality of memory cells via a plurality of bit lines, and a plurality of cache latches arranged in the first horizontal direction and respectively corresponding to the plurality of page buffer units,
• wherein the memory device is configured such that, in a data sensing period, a sensing node of a first page buffer unit sensing data stored in at least one memory cell among the plurality of memory cells among the plurality of page buffer units is actively electrically connected to a sensing node of at least a second page buffer unit from among the plurality of page buffer units.