A display device, comprising a pixel circuit array, a first GOA circuit and a second GOA circuit, the pixel circuit array comprising a plurality of pixel circuits,
- wherein the first GOA circuit and the second GOA circuit are connected to a plurality of control signal terminals in a same row of pixel circuits, and a control signal terminal electrically connected to the first GOA circuit in the plurality of control signal terminals is different from a control signal terminal electrically connected to the second GOA circuit in the plurality of control signal terminals;
- the first GOA circuit and the second GOA circuit are both connected to a first clock signal line and a second clock signal line, the first clock signal line is configured to provide a first clock signal, and the second clock signal line is configured to provide a second clock signal;
- wherein each pixel circuit of the plurality of pixel circuits comprises a light-emitting control sub-circuit and a voltage writing sub-circuit, the light-emitting control sub-circuit comprises a driving transistor, and the voltage writing sub-circuit comprises a first compensation transistor,
- a gate of the first compensation transistor is connected to a scan control signal line, a first terminal of the first compensation transistor is connected to a gate of the driving transistor, and a second terminal of the first compensation transistor is connected to a second terminal of the driving transistor;
- a first terminal of the driving transistor is connected to a power supply voltage terminal;
- the first GOA circuit is located at a side of the first clock signal line and the second clock signal line, and the second GOA circuit is located at the other side of the first clock signal line and the second clock signal line;
- the first GOA circuit, the second GOA circuit, the first clock signal line, and the second clock signal line all are located on a same side of the pixel circuit array;
- wherein each of the first GOA circuit and the second GOA circuit comprises a plurality of cascaded GOA sub-circuits,
- a signal output terminal of the GOA sub-circuit at each stage of the first GOA circuit and a signal output terminal of the GOA sub-circuit at each stage of the second GOA circuit are respectively located on two sides of the first clock signal line and the second clock signal line,
- the signal output terminal of the GOA sub-circuit at each stage of the first GOA circuit is located at a side of the first GOA circuit close to the pixel circuit array, and the signal output terminal of the GOA sub-circuit at each stage of the second GOA circuit is located at a side of the second GOA circuit away from the pixel circuit array,
- a first input terminal of the GOA sub-circuit at a first stage of the first GOA circuit is configured to receive a first initial signal, and a first input terminal of the GOA sub-circuit at a first stage of the second GOA circuit is configured to receive a second initial signal.