Horizontal and vertical assertions for validation of neuromorphic hardware

A computer program product for validating neuromorphic hardware, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform a method comprising:

• reading a description of an artificial neural network;
• constructing a directed graph of queues comprising a plurality of edges and a plurality of nodes, each of the plurality of edges corresponding to a queue of a plurality of queues and each of the plurality of nodes corresponding to a computing component of the neuromorphic hardware system, the computing components comprising at least one of a vector-matrix multiply unit, a vector-vector unit, and an activation function unit, each of the computing components being configured to compute a computing function;
• updating the graph state over a plurality of time steps according to the description of the neural network, the graph state being defined by contents of each of the plurality of queues;
• testing each of a plurality of assertions at each of the plurality of time steps, each of the plurality of assertions being a function of a subset of the graph state;
• indicating invalidity of the neural network system for each violation of one of the plurality of assertions.