Low latency and highly programmable interrupt controller unit

A system comprising:

• one or more dense compute cores;
• and
• one or more graph processing cores, wherein the graph processing cores and the dense compute cores are interconnected in a network, and each graph processing core comprises a one or more single threaded pipelines (STPs), one or more multi-threaded pipelines (MTPs), and an interrupt controller unit, each STP and MTP comprising, for each thread, a first register to hold a value indicating a currently executing program counter (PC) vector, and a second register to hold a value indicating an interrupt handler vector or an exception handler vector, wherein:
• the interrupt controller unit comprises circuitry is to:
• receive an interrupt or exception notification from an issuing pipeline;
• determine a handler vector based on the notification and of registers of the interrupt controller unit;
• and
• transmit the handler vector to the issuing pipeline;
• and
• the issuing pipeline comprises circuitry to:
• receive the handler vector from the interrupt controller unit;
• write a value in a first register into the second register;
• and
• write the handler vector into the first register.

A method to be implemented by a graph processing core, the method comprising:

• receiving, at an interrupt controller unit of the graph processing core, an interrupt or exception notification from a processing pipeline of the graph processing core;
• determining a handler vector for the interrupt or exception based on a lookup in one or more registers of the interrupt controller unit;
• writing a value in a first register of the processing pipeline into a second register of the processing pipeline, the first register indicating a vector of a next process for execution by the processing pipeline;
• writing the handler vector into the first register of the processing pipeline;
• and
• invoking, by the processing pipeline, an interrupt or exception hander based on the value written into the first register.

An apparatus comprising:

• a plurality of processing pipelines to execute one or more threads;
• an interrupt controller unit comprising:
• a plurality of addressable registers, comprising:
• one or more software programmable registers to store configuration information for the interrupt controller unit;
• registers corresponding to respective interrupt or exception types, the registers storing information identifying a handler vector for the interrupt or exception type;
• and
• circuitry to:
• configure certain of the addressable registers based on instructions executed by the plurality of processing pipelines;
• configure certain of the software programmable registers to enable or disable interrupt or exception handling by the interrupt controller unit based on a handling enable/disable instruction executed by a thread of the processing pipeline;
• and
• provide a handler vector to the processing pipelines based on interrupt or exception notifications.