Storage controller managing completion timing, and operating method thereof

A storage device comprising:

• a nonvolatile memory device;
• and
• a storage controller including:
• a command manager configured to receive a first submission queue doorbell from an external device, to fetch a first command including a first latency from the external device in response to the first submission queue doorbell, and to determine a first timing to write a first completion into the external device by adding a time period corresponding to the first latency to a time point at which the first command is fetched, the first completion indicating that the first command is completely processed;
• and
• a direct memory access (DMA) engine configured to receive a request signal requesting processing of the first command from the command manager, to transfer data, which the first command requests, based on a DMA transfer in response to the request signal, and to output a complete signal, which indicates that the first command is completely processed, to the command manager,
• wherein the command manager writes the first completion based on the complete signal from the DMA engine and based on the first timing.

A storage system comprising:

• a host device;
• a nonvolatile memory device;
• and
• a storage controller including:
• a command manager configured to receive a first submission queue doorbell from the host device, to fetch a first command including a first latency from the host device in response to the first submission queue doorbell, and to determine a first timing to write a first completion into the host device by adding a time period corresponding to the first latency to a time point at which the first command is fetched, the first completion indicating that the first command is completely processed;
• and
• a direct memory access (DMA) engine configured to receive a request signal requesting processing of the first command from the command manager, to transfer data, which the first command requests, based on a DMA transfer in response to the request signal, and to output a complete signal, which indicates that the first command is completely processed, to the command manager,
• wherein the command manager writes the first completion based on the complete signal from the DMA engine and based on the first timing.