US 12,554,499 B2 · Data compression using instruction set architecture

Abstract

In one embodiment, a computing system may set data to a first group of registers. The first group of registers may be configured to be accessed during a single operation cycle. The system may set a number of patterns to a second group of registers. Each pattern of the number of patterns may include an array of index for the data stored in the first group of registers. The system may select, for a first vector register associated with a vector engine, a first pattern from the patterns stored in the second group of registers. The system may load a first portion of the data from the first group of registers to the first vector register based on the first pattern selected for the first vector register from the patterns stored in the second group of registers.

Claims19

Dependent claims

A processor comprising:

an instruction set architecture configured to compress uncompressed input data, wherein the instruction set architecture comprises:
a compression module configured to autonomously and without involvement of software instructions:
read the uncompressed input data from a memory bank;
remove zero data elements from the uncompressed input data;
and
write compressed output data to the memory bank;
a counter register configured to count a number of non-zero data elements in the uncompressed input data;
and
one or more instructions configured to execute directly in hardware on the processor in machine code defined for the instruction set architecture, wherein the one or more instructions comprise a first instruction configured to set the compression module to (1) receive the uncompressed input data and (2) remove the zero data elements from the uncompressed input data.

6 more elements

Dependencies are inferred from the claim text.

Data compression using instruction set architecture

Life of this patent

Data compression using instruction set architecture

Life of this patent

Abstract

Claims19