Decoder having multiple stages of adders to decode delta encoded data

A decompressor unit implemented in a cache memory having a cache memory cell array, comprising:

• a decompressor to decompress a compressed chunk of encoded items stored in the cache memory cell array to produce an uncompressed encoded chunk of the encoded items, wherein the encoded items are formed using delta encoding and include a plurality of deltas of neighbors of sequential source items;
• and
• a decoder including:
• a first stage of adder circuits to add, in parallel, pairs of the encoded items;
• and
• at least one successive stage of adder circuits to add, in parallel in each stage of adder circuits, pairs of outputs multiple hops away from a previous stage of adder circuits, wherein each successive stage has fewer adder circuits than the previous stage of adder circuits to add fewer outputs than at the previous stage of adder circuits, and wherein output from a last of the at least one successive stage comprises the sequential source items.