Multi-node computing system
AssigneeSamsung Electronics Co., Ltd.
InventorEric Richard Borch
Life of this patent
Estimating the term…
Abstract
A multi-node computing system. In some embodiments, the system includes: a first compute board, a second compute board, a plurality of compute elements, a plurality of memories, a first network plane connecting the first compute board and the second compute board, and a second network plane connecting the first compute board and the second compute board. The plurality of memories may store instructions that, when executed by the plurality of compute elements, cause the plurality of compute elements to: determine that a criterion for deactivating the first network plane is met, and deactivate the first network plane.
Claims20
A system, comprising:
- a first compute board;
- a second compute board;
- a plurality of compute elements;
- a plurality of memories;
- a first network plane connecting the first compute board and the second compute board;
- and
- a second network plane connecting the first compute board and the second compute board,
- the plurality of memories storing instructions that, when executed by the plurality of compute elements, cause the plurality of compute elements to:
- determine that a criterion for deactivating the first network plane is met;
- and
- deactivate the first network plane.
A method, comprising:
- determining, by a plurality of compute elements, that a criterion for deactivating a first network plane is met;
- and
- deactivating the first network plane,
- wherein the compute elements are part of a computing system comprising:
- a first compute board;
- a second compute board;
- the plurality of compute elements;
- a plurality of memories;
- the first network plane;
- and
- a second network plane connecting the first compute board and the second compute board, and
- wherein the first network plane connects the first compute board and the second compute board.
A system, comprising:
- a first compute board;
- a second compute board;
- a plurality of means for processing;
- a plurality of memories;
- a first network plane connecting the first compute board and the second compute board;
- and
- a second network plane connecting the first compute board and the second compute board,
- the plurality of memories storing instructions that, when executed by the plurality of means for processing, cause the plurality of means for processing to:
- determine that a criterion for deactivating the first network plane is met;
- and
- deactivate the first network plane.
Dependencies are inferred from the claim text.